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* Special epilogue for vararg functions. We cannot do a pop to pc becauseEvan Cheng2007-02-012-5/+24
| | | | | | | | | | | there follows a sp increment for the va register save region. Instead issue a separate pop to another register, increment sp, and then return: pop {r4, r5, r6, r7} pop {r3} add sp, #3 * 4 bx r3 llvm-svn: 33739
* Pessmistically assume the .align 2 before the first constpool entry addsEvan Cheng2007-02-011-2/+12
| | | | | | two bytes padding. llvm-svn: 33734
* Possible JT improvements.Evan Cheng2007-02-011-3/+43
| | | | llvm-svn: 33733
* Fix CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.llChris Lattner2007-02-012-1/+7
| | | | llvm-svn: 33732
* Don't emit unnecessary .align directive.Evan Cheng2007-01-311-3/+1
| | | | llvm-svn: 33729
* Handle an interesting corner case: the constpool_entry being reference is twoEvan Cheng2007-01-311-2/+2
| | | | | | | | | instructions away, i.e. its address is equal to PC. %r0 = tLDRpci <cp#0> bx CONSTPOOL_ENTRY 0 <cp#0>, 4 llvm-svn: 33728
* Don't want to add FramePtr to callee save spill list twice.Evan Cheng2007-01-311-8/+2
| | | | llvm-svn: 33727
* Darwin ABI requires FP to point to stack slot of prev FP.Evan Cheng2007-01-311-3/+14
| | | | llvm-svn: 33724
* Add entry.Evan Cheng2007-01-311-0/+4
| | | | llvm-svn: 33723
* Thumb add sp, #imm requires the immediate value be multiple of 4. For now,Evan Cheng2007-01-311-2/+6
| | | | | | change preferred alignment of short, byte, bool to 4. llvm-svn: 33722
* Update comment.Evan Cheng2007-01-311-1/+1
| | | | llvm-svn: 33721
* Dead comment.Evan Cheng2007-01-311-1/+0
| | | | llvm-svn: 33719
* Thumb asm syntax does not want 's' suffix for flag setting opcodes.Evan Cheng2007-01-311-2/+2
| | | | llvm-svn: 33717
* When determining whether a pc relative branch / load displacement fits in theEvan Cheng2007-01-311-27/+42
| | | | | | instruction field, adjust it for PC value (4 for thumb, 8 for arm). llvm-svn: 33711
* A relatively simple PPC optimization.Chris Lattner2007-01-311-0/+27
| | | | llvm-svn: 33709
* Some comments.Evan Cheng2007-01-311-2/+6
| | | | llvm-svn: 33707
* ConstPool island bug: watch out for cases where UserMI is the last MI of the BB.Evan Cheng2007-01-311-4/+16
| | | | llvm-svn: 33706
* ARM fix: Miscompilation when frame pointer can't be eliminated. ↵Lauro Ramos Venancio2007-01-311-10/+9
| | | | | | Uninitialized frame pointer register is used. llvm-svn: 33703
* Specify the right CC for comparison libcalls.Evan Cheng2007-01-311-0/+20
| | | | llvm-svn: 33702
* Observe -soft-float.Evan Cheng2007-01-311-3/+4
| | | | llvm-svn: 33699
* - Added Thumb constpool island support.Evan Cheng2007-01-311-24/+17
| | | | | | | - Islands are inserted right after the user MI since thumb LDR cannot encode negative offset. llvm-svn: 33690
* During PEI, if the immediate value of sp + offset is too large (i.e. somethingEvan Cheng2007-01-301-21/+102
| | | | | | | that would require > 3 instructions to materialize), load the immediate from a constpool entry. llvm-svn: 33667
* - Fix codegen for pc relative constant (e.g. JT) in thumb mode:Evan Cheng2007-01-307-47/+96
| | | | | | | | | | | | | | | | | | | .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4)) LPCRELL0: add r1, pc, #PCRELV0 This is not legal since add r1, pc, #c requires the constant be a multiple of 4. Do the following instead: .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4)) LPCRELL0: mov r1, #PCRELV0 add r1, pc - In thumb mode, it's not possible to use .set generate a pc relative stub address. The stub is ARM code which is in a different section from the thumb code. Load the value from a constpool instead. - Some asm printing clean up. llvm-svn: 33664
* For PR1136: Rename GlobalVariable::isExternal as isDeclaration to avoidReid Spencer2007-01-3010-23/+23
| | | | | | confusion with external linkage types. llvm-svn: 33663
* Copy and paste bug.Evan Cheng2007-01-301-1/+11
| | | | llvm-svn: 33658
* Darwin -static should codegen static ctors / dtors to .constructor / ↵Evan Cheng2007-01-306-9/+47
| | | | | | .destructor sections. llvm-svn: 33657
* Misseed thumb jumptable branch.Evan Cheng2007-01-301-0/+1
| | | | llvm-svn: 33656
* In thumb mode, round up stack frame size to multiple of 4 since add/subEvan Cheng2007-01-301-115/+124
| | | | | | sp, imm instructions implicitly multiply the offset by 4. llvm-svn: 33653
* Thumb eliminateFrameIndex fixes.Evan Cheng2007-01-301-8/+27
| | | | llvm-svn: 33652
* Change the operand orders to t_addrmode_s* to make it easier to morphEvan Cheng2007-01-303-32/+26
| | | | | | | instructions that use these address modes to instructions that use t_addrmode_sp. llvm-svn: 33651
* - In thumb mode, if size of MachineFunction is >= 2048, force LR to beEvan Cheng2007-01-303-41/+123
| | | | | | | | | | | | | spilled (if it is not already). - If LR is spilled, use BL to implement far jumps. LR is not used as a GPR in thumb mode so it can be clobbered if it is properly spilled / restored in prologue / epilogue. - If LR is force spilled but no far jump has been emitted, try undo'ing the spill by: push lr -> delete pop pc -> bx lr llvm-svn: 33650
* Use BL to implement Thumb far jumps.Evan Cheng2007-01-301-0/+3
| | | | llvm-svn: 33649
* Factor GetInstSize() out of constpool island pass.Evan Cheng2007-01-293-70/+84
| | | | llvm-svn: 33644
* Only gather frame info if debug or eh.Jim Laskey2007-01-292-4/+4
| | | | llvm-svn: 33639
* Finish off bug 680, allowing targets to custom lower frame and returnNate Begeman2007-01-298-34/+42
| | | | | | address nodes. llvm-svn: 33636
* We'd still like to register allocate r2 on darwin before the callee-saveNate Begeman2007-01-291-6/+6
| | | | | | regs. llvm-svn: 33635
* rename flagJim Laskey2007-01-291-1/+1
| | | | llvm-svn: 33634
* Comment.Evan Cheng2007-01-291-1/+1
| | | | llvm-svn: 33633
* Remember if LR register has been spilled in this function.Evan Cheng2007-01-292-5/+17
| | | | llvm-svn: 33632
* Save all registers by default, as they can be used to pass parametersAnton Korobeynikov2007-01-291-13/+11
| | | | | | for "inreg" calls llvm-svn: 33631
* Update some of the llvm in the readmeNate Begeman2007-01-291-25/+23
| | | | llvm-svn: 33630
* Flag to control exception handling.Jim Laskey2007-01-291-0/+6
| | | | llvm-svn: 33628
* Landing pad-less eh for PPC.Jim Laskey2007-01-294-8/+10
| | | | llvm-svn: 33622
* Implement use of new IntrinsicLowering interface.Reid Spencer2007-01-291-4/+9
| | | | llvm-svn: 33619
* Fix compile error "jump to case label crosses initialization".Nick Lewycky2007-01-281-5/+6
| | | | | | What compiler are people using that accepts this code? llvm-svn: 33603
* Propagate changes from my local tree. This patch includes:Anton Korobeynikov2007-01-287-775/+383
| | | | | | | | | | | | | | | | | | | | | | 1. New parameter attribute called 'inreg'. It has meaning "place this parameter in registers, if possible". This is some generalization of gcc's regparm(n) attribute. It's currently used only in X86-32 backend. 2. Completely rewritten CC handling/lowering code inside X86 backend. Merged stdcall + c CCs and fastcall + fast CC. 3. Dropped CSRET CC. We cannot add struct return variant for each target-specific CC (e.g. stdcall + csretcc and so on). 4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in on first attribute has meaning 'This is hidden pointer to structure return. Handle it gently'. 5. Fixed small bug in llvm-extract + add new feature to FunctionExtraction pass, which relinks all internal-linkaged callees from deleted function to external linkage. This will allow further linking everything together. NOTEs: 1. Documentation will be updated soon. 2. llvm-upgrade should be improved to translate csret => sret. Before this, there will be some unexpected test fails. llvm-svn: 33597
* Make d'tor out-of-line.Bill Wendling2007-01-272-1/+2
| | | | llvm-svn: 33585
* Return an X86ELFWriterInfo object.Bill Wendling2007-01-271-1/+6
| | | | llvm-svn: 33574
* X86 implementation of the TargetELFWriterInfo class.Bill Wendling2007-01-272-0/+46
| | | | llvm-svn: 33571
* New entry.Evan Cheng2007-01-271-0/+4
| | | | llvm-svn: 33569
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