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* R600/SI: Default to no single precision denormals.Matt Arsenault2014-07-141-1/+9
| | | | llvm-svn: 213017
* [X86] Specify all TSFlags bit-offsets symbolicallyAdam Nemet2014-07-141-3/+6
| | | | | | | | | | | | | | | No functional change. The offsets for the other bitfields are specified symbolically. I need to increase the size for one of the earlier fields which is easier after this cleanup. Why these bits are relative to VEXShift is a bit strange but that is for another cleanup. I made sure that the values for the enums are unchanged after this change. llvm-svn: 213011
* CodeGen: Stick constant pool entries in COMDAT sections for WinCOFFDavid Majnemer2014-07-148-5/+100
| | | | | | | | | | | | | | | | COFF lacks a feature that other object file formats support: mergeable sections. To work around this, MSVC sticks constant pool entries in special COMDAT sections so that each constant is in it's own section. This permits unused constants to be dropped and it also allows duplicate constants in different translation units to get merged together. This fixes PR20262. Differential Revision: http://reviews.llvm.org/D4482 llvm-svn: 213006
* X86: correct 64-bit atomics on 32-bitSaleem Abdulrasool2014-07-141-12/+8
| | | | | | | | | | | | | | | | We would emit a libcall for a 64-bit atomic on x86 after SVN r212119. This was due to the misuse of hasCmpxchg16 to indicate if cmpxchg8b was supported on a 32-bit target. They were added at different times and would result in the border condition being mishandled. This fixes the border case to emit the cmpxchg8b instruction for 64-bit atomic operations on x86 at the cost of restoring a long-standing bug in the codegen. We emit a cmpxchg8b on all x86 targets even where the CPU does not support this instruction (pre-Pentium CPUs). Although this bug should be fixed, this was present prior to SVN r212119 and this change, so this is not really introducing a regression. llvm-svn: 212956
* X86: remove temporary atomicrmw used during lowering.Tim Northover2014-07-141-2/+5
| | | | | | | | | | | We construct a temporary "atomicrmw xchg" instruction when lowering atomic stores for widths that aren't supported natively. This isn't on the top-level worklist though, so it won't be removed automatically and we have to do it ourselves once that itself has been lowered. Thanks Saleem for pointing this out! llvm-svn: 212948
* Re-commit: [mips] Correct section alignments and EntrySizes for .bss, .text, ↵Daniel Sanders2014-07-141-5/+23
| | | | | | | | .data, .reginfo, .MIPS.options, and .MIPS.abiflags The lld tests will temporarily fail again but Simon Atanasyan will commit a fix for those shortly. llvm-svn: 212946
* Revert: [mips] Correct section alignments and EntrySizes for .bss, .text, ↵Daniel Sanders2014-07-141-23/+5
| | | | | | | | .data, .reginfo, .MIPS.options, and .MIPS.abiflags This commit causes multiple lld tests to fail. Reverting while I investigate the issue. llvm-svn: 212945
* [mips] Correct section alignments and EntrySizes for .bss, .text, .data, ↵Daniel Sanders2014-07-141-5/+23
| | | | | | | | | | | | | | | | | | .reginfo, .MIPS.options, and .MIPS.abiflags Summary: .bss, .text, and .data are at least 16-byte aligned. .reginfo is 4-byte aligned and has a 24-byte EntrySize. .MIPS.abiflags has an 24-byte EntrySize. .MIPS.options is 8-byte aligned and has 1-byte EntrySize. Using a 1-byte EntrySize for .MIPS.options seems strange because the records are neither 1-byte long nor fixed-length but this matches the value that GAS emits. Differential Revision: http://reviews.llvm.org/D4487 llvm-svn: 212939
* [mips] For the FP64A ABI, odd-numbered double-precision moves must not use ↵Daniel Sanders2014-07-145-23/+119
| | | | | | | | | | | | | | | | | | | | | mtc1/mfc1. Summary: This is because the FP64A the hardware will redirect 32-bit reads/writes from/to odd-numbered registers to the upper 32-bits of the corresponding even register. In effect, simulating FR=0 mode when FR=0 mode is not available. Unfortunately, we have to make the decision to avoid mfc1/mtc1 before register allocation so we currently do this for even registers too. FPXX has a similar requirement on 32-bit architectures that lack mfhc1/mthc1 so this patch also handles the affected moves from the FPU for FPXX too. Moves to the FPU were supported by an earlier commit. Differential Revision: http://reviews.llvm.org/D4484 llvm-svn: 212938
* [mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and ↵Daniel Sanders2014-07-143-25/+13
| | | | | | | | | | | | | | FP64 moves Summary: This is similar to r210771 which did the same thing for MTHC1. Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the wrong definitions. Differential Revision: http://reviews.llvm.org/D4483 llvm-svn: 212936
* AArch64: remove unnecessary pseudo-instruction.Tim Northover2014-07-142-15/+3
| | | | | | | Sufficiently twisted use of TableGen lets us write patterns directly for f16 (as an i16 promoted to i32) -> f32 conversion. llvm-svn: 212933
* [mips] Correct the AFL_FLAGS1_ODDSPREG flag in .MIPS.abiflags when no ↵Daniel Sanders2014-07-142-3/+4
| | | | | | | | '.module oddspreg' is used Differential Revision: http://reviews.llvm.org/D4486 llvm-svn: 212932
* [mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI isSasa Stankovic2014-07-146-12/+84
| | | | | | | | | | | | | | | enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1) This prevents the upper 32-bits of a double precision value from being moved to the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure that the code generated executes correctly regardless of the current FPU mode. MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue to use dmtc1. Differential Revision: http://reviews.llvm.org/D4465 llvm-svn: 212930
* NVPTX/LLVMBuild.txt: Add "Scalar" to required_libraries. It is really ↵NAKAMURA Takumi2014-07-141-1/+1
| | | | | | referenced. llvm-svn: 212918
* MC: make DWARF and Windows unwinding handling more similarSaleem Abdulrasool2014-07-131-2/+2
| | | | | | | | Rename member variables and functions for the MCStreamer for DWARF-like unwinding management. Rename the Windows ones as well and make the naming and handling similar across the two. No functional change intended. llvm-svn: 212912
* Remove unused includeMatt Arsenault2014-07-131-1/+0
| | | | llvm-svn: 212898
* R600: Use range for and fix missing consts.Matt Arsenault2014-07-132-29/+20
| | | | llvm-svn: 212897
* R600: Make ShaderType privateMatt Arsenault2014-07-139-34/+45
| | | | llvm-svn: 212896
* R600: Add option to disable promote allocaMatt Arsenault2014-07-134-5/+24
| | | | | | | This can make writing some tests harder, so add a flag to disable it. llvm-svn: 212893
* AArch64: add support for llvm.aarch64.hint intrinsicSaleem Abdulrasool2014-07-121-11/+17
| | | | | | | | | | | This adds a llvm.aarch64.hint intrinsic to mirror the llvm.arm.hint in order to support the various hint intrinsic functions in the ACLE. Add an optional pattern field that permits the subclass to specify the pattern that matches the selection. The intrinsic pattern is set as mayLoad, mayStore, so overload the value for the definition of the hint instruction. llvm-svn: 212883
* Revert "[FastISel][X86] Implement the FastLowerIntrinsicCall hook."Juergen Ributzka2014-07-111-38/+42
| | | | | | This reverts commit r212851, because it broke the memset lowering. llvm-svn: 212855
* [FastISel][X86] Implement the FastLowerIntrinsicCall hook.Juergen Ributzka2014-07-111-42/+38
| | | | | | | Rename X86VisitIntrinsicCall -> FastLowerIntrinsicCall, which effectively implements the target hook. llvm-svn: 212851
* [PowerPC] Fix invalid displacement created by LocalStackAllocUlrich Weigand2014-07-111-10/+10
| | | | | | | | | | | | | | | | | | | | | | | This commit fixes a bug in PPCRegisterInfo::isFrameOffsetLegal that could result in the LocalStackAlloc pass creating an MI instruction out-of-range displacement: %vreg17<def> = LD 33184, %vreg31; mem:LD8[%g](align=32) %G8RC:%vreg17 G8RC_and_G8RC_NOX0:%vreg31 (In final assembler output the top bits are stripped off, resulting in a negative offset loading from below the stack pointer.) Common code expects the isFrameOffsetLegal routine to verify whether adding a given offset to the offset already present in the instruction results in a valid displacement. However, on PowerPC the routine did not take the already present instruction offset into account. This commit fixes isFrameOffsetLegal to add the instruction offset, and updates a local caller (needsFrameBaseReg) to no longer add the instruction offset itself before calling isFrameOffsetLegal. Reviewed by Hal Finkel. llvm-svn: 212832
* R600/SI: Use i32 vectors for resources and samplersMarek Olsak2014-07-112-5/+5
| | | | | | | | This affects new intrinsics only. What surprises me is that v32i8 still works. llvm-svn: 212831
* R600/SI: add sample and image intrinsics exposing all instruction fieldsMarek Olsak2014-07-112-48/+192
| | | | | | | | | | | We need the intrinsics with offsets, so why not just add them all. The R128 parameter will also be useful for reducing SGPR usage. GL_ARB_image_load_store also adds some image GLSL modifiers like "coherent", so Mesa will probably translate those to slc, glc, etc. When LLVM 3.5 is released, I'll switch Mesa to these new intrinsics. llvm-svn: 212830
* R600/SI: fix shadow mapping for 1D and 2D array texturesMarek Olsak2014-07-111-1/+1
| | | | | | | It was conflicting with def TEX_SHADOW_ARRAY, which also handles them. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 212829
* ARM: Allow __fp16 as a function arg or return type for AArch64Oliver Stannard2014-07-112-3/+11
| | | | | | | ACLE 2.0 allows __fp16 to be used as a function argument or return type. This enables this for AArch64. llvm-svn: 212812
* [X86] Fix the inversion of low and high bits for the lowering of MUL_LOHI.Quentin Colombet2014-07-111-9/+41
| | | | | | | | Also add a few comments. <rdar://problem/17581756> llvm-svn: 212808
* [X86] AVX512: Improve readability of isCDisp8Adam Nemet2014-07-111-3/+12
| | | | | | | | No functional change. As I was trying to understand this function, I found that variables were reused with confusing names and the broadcast case was a bit too implicit. Hopefully, this is an improvement. llvm-svn: 212795
* [X86] AVX512: Simplify logic in isCDisp8Adam Nemet2014-07-111-6/+6
| | | | | | | | | | | | It was computing the VL/n case as: MemObjSize = VectorByteSize / ElemByteSize / Divider * ElemByteSize ElemByteSize not only falls out but VectorByteSize/Divider now actually matches the definition of VL/n. Also some formatting fixes. llvm-svn: 212794
* R600: Implement float to long/ulongJan Vesely2014-07-103-2/+18
| | | | | | | | | | | | | | Use alg. from LegalizeDAG.cpp Move Expand setting to SIISellowering v2: Extend existing tests instead of creating new ones v3: use separate LowerFPTOSINT function v4: use TargetLowering::expandFP_TO_SINT add comment about using FP_TO_SINT for uints Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 212773
* Use the integrated assembler by default on OpenBSD.Brad Smith2014-07-101-1/+2
| | | | llvm-svn: 212771
* [mips] Emit two CFI offset directives per double precision SDC1/LDC1Zoran Jovanovic2014-07-102-4/+21
| | | | | | | instead of just one for FR=1 registers Differential Revision: http://reviews.llvm.org/D4310 llvm-svn: 212769
* [X86] Mark pseudo instruction TEST8ri_NOEREX as hasSIdeEffects=0.Akira Hatanaka2014-07-102-2/+5
| | | | | | | | | Also, add a case clause in X86InstrInfo::shouldScheduleAdjacent to enable macro-fusion. <rdar://problem/15680770> llvm-svn: 212747
* Make it possible for the Subtarget to change between functionEric Christopher2014-07-109-56/+57
| | | | | | | | passes in the mips back end. This, unfortunately, required a bit of churn in the various predicates to use a pointer rather than a reference. llvm-svn: 212744
* Mips: Silence a -Wcovered-switch-defaultDavid Majnemer2014-07-101-2/+2
| | | | | | | | | Remove a default label which covered no enumerators, replace it with a llvm_unreachable. No functionality changed. llvm-svn: 212729
* [mips] Added FPXX modeless calling convention.Zoran Jovanovic2014-07-105-1/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D4293 llvm-svn: 212726
* [AArch64] Add logical alias instructions to MC AsmParserArnaud A. de Grandmaison2014-07-103-14/+76
| | | | | | | | | | | | | | | | This patch teaches the AsmParser to accept some logical+immediate instructions and convert them as shown: bic Rd, Rn, #imm -> and Rd, Rn, #~imm bics Rd, Rn, #imm -> ands Rd, Rn, #~imm orn Rd, Rn, #imm -> orr Rd, Rn, #~imm eon Rd, Rn, #imm -> eor Rd, Rn, #~imm Those instructions are an alternate syntax available to assembly coders, and are needed in order to support code already compiling with some other assemblers. For example, the bic construct is used by the linux kernel. llvm-svn: 212722
* AArch64: correctly fast-isel i8 & i16 multipliesTim Northover2014-07-101-0/+1
| | | | | | | | We were asking for a register for type i8 or i16 which caused an assert. rdar://problem/17620015 llvm-svn: 212718
* [mips] Add support for -modd-spreg/-mno-odd-spregDaniel Sanders2014-07-1011-98/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When -mno-odd-spreg is in effect, 32-bit floating point values are not permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit floating point comparison results from being written to odd registers. This option has three purposes: * It allows support for certain MIPS implementations such as loongson-3a that do not allow the use of odd registers for single precision arithmetic. * When using -mfpxx, -mno-odd-spreg is the default and this allows us to statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1 instructions to/from odd registers are guaranteed not to appear for any reason. Once this has been established, the user can then re-enable -modd-spreg to regain the use of all 32 single-precision registers. * When using -mfp64 and -mno-odd-spreg together, an O32 extension named O32 FP64A is used as the ABI. This is intended to provide almost all functionality of an FR=1 processor but can also be executed on a FR=0 core with the assistance of a hardware compatibility mode which emulates FR=0 behaviour on an FR=1 processor. * Added '.module oddspreg' and '.module nooddspreg' each of which update the .MIPS.abiflags section appropriately * Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller doesn't have to remember to do it. * MipsABIFlags now calculates the flags1 and flags2 member on demand rather than trying to maintain them in the same format they will be emitted in. There is one portion of the -mfp64 and -mno-odd-spreg combination that is not implemented yet. Moves to/from odd-numbered double-precision registers must not use mtc1. I will fix this in a follow-up. Differential Revision: http://reviews.llvm.org/D4383 llvm-svn: 212717
* [x32] Add AsmBackend for X32 which uses ELF32 with x86_64 (the author is ↵Zinovy Nis2014-07-101-0/+14
| | | | | | | | | | Pavel Chupin). This is minimal change for backend required to have "hello world" compiled and working on x32 target (x86_64-linux-gnux32). More patches for x32 will follow. Differential Revision: http://reviews.llvm.org/D4181 llvm-svn: 212716
* [SystemZ] Use SystemZCallingConv.td to define callee-saved registersRichard Sandiford2014-07-105-16/+23
| | | | | | Just a clean-up. No behavioral change intended. llvm-svn: 212711
* [SystemZ] Tweak instruction format classificationsRichard Sandiford2014-07-102-53/+43
| | | | | | | | | | There's no real need to have Shift as a separate format type from Binary. The comments for other format types were too specific and in some cases no longer accurate. Just a clean-up, no behavioral change intended. llvm-svn: 212707
* [x86] Add another combine that is particularly useful for the new vectorChandler Carruth2014-07-101-0/+41
| | | | | | | | | | shuffle lowering: match shuffle patterns equivalent to an unpcklwd or unpckhwd instruction. This allows us to use generic lowering code for v8i16 shuffles and match the unpack pattern late. llvm-svn: 212705
* [SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRARichard Sandiford2014-07-101-0/+7
| | | | | | | These instructions aren't used for codegen since the original L*DB instructions are suitable for fround. llvm-svn: 212703
* [SystemZ] Avoid using i8 constants for immediate fieldsRichard Sandiford2014-07-105-58/+54
| | | | | | | | | | | | Immediate fields that have no natural MVT type tended to use i8 if the field was small enough. This was a bit confusing since i8 isn't a legal type for the target. Fields for short immediates in a 32-bit or 64-bit operation use i32 or i64 instead, so it would be better to do the same for all fields. No behavioral change intended. llvm-svn: 212702
* [SystemZ] Fix FPR dwarf numberingRichard Sandiford2014-07-101-1/+24
| | | | | | | | The dwarf FPR numbers are supposed to have the order F0, F2, F4, F6, F1, F3, F5, F7, F8, etc., which matches the pairing of registers for long doubles. E.g. a long double stored in F0 is paired with F2. llvm-svn: 212701
* Make it possible for ints/floats to return different values from ↵Daniel Sanders2014-07-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | getBooleanContents() Summary: On MIPS32r6/MIPS64r6, floating point comparisons return 0 or -1 but integer comparisons return 0 or 1. Updated the various uses of getBooleanContents. Two simplifications had to be disabled when float and int boolean contents differ: - ScalarizeVecRes_VSELECT except when the kind of boolean contents is trivially discoverable (i.e. when the condition of the VSELECT is a SETCC node). - visitVSELECT (select C, 0, 1) -> (xor C, 1). Come to think of it, this one could test for the common case of 'C' being a SETCC too. Preserved existing behaviour for all other targets and updated the affected MIPS32r6/MIPS64r6 tests. This also fixes the pi benchmark where the 'low' variable was counting in the wrong direction because it thought it could simply add the result of the comparison. Reviewers: hfinkel Reviewed By: hfinkel Subscribers: hfinkel, jholewinski, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D4389 llvm-svn: 212697
* [x86] Expand the target DAG combining for PSHUFD nodes to be able toChandler Carruth2014-07-101-1/+34
| | | | | | | | | | combine into half-shuffles through unpack instructions that expand the half to a whole vector without messing with the dword lanes. This fixes some redundant instructions in splat-like lowerings for v16i8, which are now getting to be *really* nice. llvm-svn: 212695
* [x86] Tweak the v16i8 single input special case lowering for shufflesChandler Carruth2014-07-101-34/+44
| | | | | | | | | | | | | | | | | | | that splat i8s into i16s. Previously, we would try much too hard to arrange a sequence of i8s in one half of the input such that we could unpack them into i16s and shuffle those into place. This isn't always going to be a cheaper i8 shuffle than our other strategies. The case where it is always going to be cheaper is when we can arrange all the necessary inputs into one half using just i16 shuffles. It happens that viewing the problem this way also makes it much easier to produce an efficient set of shuffles to move the inputs into one half and then unpack them. With this, our splat code gets one step closer to being not terrible with the new experimental lowering strategy. It also exposes two combines missing which I will add next. llvm-svn: 212692
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