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* [NVPTX] Implement custom lowering of loads/stores for i1Justin Holewinski2012-11-142-2/+61
| | | | | | | | | Loads from i1 become loads from i8 followed by trunc Stores to i1 become zext to i8 followed by store to i8 Fixes PR13291 llvm-svn: 167948
* X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.Jim Grosbach2012-11-142-9/+42
| | | | | | | | | | When an instruction as written requires 32-bit mode and we're assembling in 64-bit mode, or vice-versa, issue a more specific diagnostic about what's wrong. rdar://12700702 llvm-svn: 167937
* Set FFLOOR of vectors to expand to keep intruction selection from failing.Craig Topper2012-11-141-0/+1
| | | | llvm-svn: 167922
* Factor out an overly replicated typecast. No functional change.Craig Topper2012-11-141-65/+66
| | | | llvm-svn: 167916
* Set FFLOOR for vectors to expand on CellSPU to keep instruction selection ↵Craig Topper2012-11-141-1/+2
| | | | | | from failing on llvm.floor of a vector. llvm-svn: 167914
* Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov2012-11-145-20/+38
| | | | | | | | Do some cleanup of the code while here. Inspired by patch by Logan Chien! llvm-svn: 167904
* Add (some) PowerPC TLS relocation types to ELF.h andUlrich Weigand2012-11-131-2/+18
| | | | | | | generate them from PPCELFObjectWriter::getRelocTypeInner as appropriate. llvm-svn: 167864
* Fix wrong PowerPC instruction opcodes for:Ulrich Weigand2012-11-132-4/+4
| | | | | | | | - lwaux - lhzux - stbu llvm-svn: 167863
* Fix wrong PowerPC instruction encodings due toUlrich Weigand2012-11-132-10/+10
| | | | | | | | | operand field name mismatches in: - AForm_3 (fmul, fmuls) - XFXForm_5 (mtcrf) - XFLForm (mtfsf) llvm-svn: 167862
* Fix instruction encoding for "bd(n)z" on PowerPC,Ulrich Weigand2012-11-133-14/+15
| | | | | | by using a new instruction format BForm_1. llvm-svn: 167861
* Fix instruction encoding for "isel" on PowerPC,Ulrich Weigand2012-11-133-2/+22
| | | | | | using a new instruction format AForm_4. llvm-svn: 167860
* X86: when constructing VZEXT_LOAD from other loads, makes sure its outputManman Ren2012-11-131-0/+12
| | | | | | | | | | | chain is correctly setup. As an example, if the original load must happen before later stores, we need to make sure the constructed VZEXT_LOAD is constrained to be before the stores. rdar://12684358 llvm-svn: 167859
* misched: Allow subtargets to enable misched and dependent options.Andrew Trick2012-11-131-0/+4
| | | | | | | | | | | | This allows me to begin enabling (or backing out) misched by default for one subtarget at a time. To run misched we typically want to: - Disable SelectionDAG scheduling (use the source order scheduler) - Enable more aggressive coalescing (until we decide to always run the coalescer this way) - Enable MachineScheduler pass itself. Disabling PostRA sched may follow for some subtargets. llvm-svn: 167826
* Test commit.Jyotsna Verma2012-11-131-0/+1
| | | | | | Add a blank line. llvm-svn: 167819
* misched: Target-independent support for load/store clustering.Andrew Trick2012-11-121-0/+6
| | | | | | | | | | This infrastructure is generally useful for any target that wants to strongly prefer two instructions to be adjacent after scheduling. A following checkin will add target-specific hooks with unit tests. Then this feature will be enabled by default with misched. llvm-svn: 167742
* Make TOC order deterministic by using MapVector instead of DenseMap.Ulrich Weigand2012-11-121-3/+3
| | | | llvm-svn: 167737
* Remove unused field.Eric Christopher2012-11-121-1/+0
| | | | llvm-svn: 167719
* Fix PR14314Michael Liao2012-11-121-2/+2
| | | | | | | - Fix operand order for atomic sub, where the minuend is the value loaded from memory and the subtrahend is the parameter specified. llvm-svn: 167718
* [NVPTX] Add more precise PTX/SM target attributesJustin Holewinski2012-11-124-11/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each SM and PTX version is modeled as a subtarget feature/CPU. Additionally, PTX 3.1 is added as the default PTX version to be out-of-the-box compatible with CUDA 5.0. Available CPUs for this target: sm_10 - Select the sm_10 processor. sm_11 - Select the sm_11 processor. sm_12 - Select the sm_12 processor. sm_13 - Select the sm_13 processor. sm_20 - Select the sm_20 processor. sm_21 - Select the sm_21 processor. sm_30 - Select the sm_30 processor. sm_35 - Select the sm_35 processor. Available features for this target: ptx30 - Use PTX version 3.0. ptx31 - Use PTX version 3.1. sm_10 - Target SM 1.0. sm_11 - Target SM 1.1. sm_12 - Target SM 1.2. sm_13 - Target SM 1.3. sm_20 - Target SM 2.0. sm_21 - Target SM 2.1. sm_30 - Target SM 3.0. sm_35 - Target SM 3.5. llvm-svn: 167699
* Move some helper methods to being static functions in the implementation file.Craig Topper2012-11-112-20/+7
| | | | llvm-svn: 167696
* Use the isTruncFree and isZExtFree API to figure out of these operations are ↵Nadav Rotem2012-11-111-2/+10
| | | | | | free. Thanks Andy! llvm-svn: 167685
* Remove unnecessary subtraction and addition by 1 around a couple for loops.Craig Topper2012-11-101-6/+6
| | | | llvm-svn: 167673
* Tidy up spacing. No functional change.Craig Topper2012-11-101-4/+4
| | | | llvm-svn: 167671
* Removed unimplemented method declaration.Craig Topper2012-11-101-1/+0
| | | | llvm-svn: 167670
* Simplify custom emitter code for pcmp(e/i)str(i/m) and make the helper ↵Craig Topper2012-11-102-96/+42
| | | | | | functions static. llvm-svn: 167669
* Add more functions to the target library information.Meador Inge2012-11-101-0/+18
| | | | | | | | | | | In the process of migrating optimizations from the simplify-libcalls pass to the instcombine pass I noticed that a few functions are missing from the target library information. These functions need to be available for querying in the instcombine library call simplifiers. More functions will probably be added in the future as more simplifiers are migrated to instcombine. llvm-svn: 167659
* Disable the Thumb no-return call optimization:Evan Cheng2012-11-103-47/+2
| | | | | | | | | | | | mov lr, pc b.w _foo The "mov" instruction doesn't set bit zero to one, it's putting incorrect value in lr. It messes up backtraces. rdar://12663632 llvm-svn: 167657
* Cleanup pcmp(e/i)str(m/i) instruction definitions and load folding support.Craig Topper2012-11-104-161/+192
| | | | llvm-svn: 167652
* [NVPTX] Use ABI alignment for parameters when alignment is not specified.Justin Holewinski2012-11-091-0/+3
| | | | | | Affects SM 2.0+. Fixes bug 13324. llvm-svn: 167646
* Add ARM TARGET2 relocation. The testcase will follow with actualy use-case.Anton Korobeynikov2012-11-091-0/+3
| | | | | | Based on the patch by Logan Chien! llvm-svn: 167633
* Switch FreeBSD/i386 back to 4byte stack alignment. This partiallyRoman Divacky2012-11-091-3/+3
| | | | | | reverts r126226. llvm-svn: 167632
* Revert r167620; this can be implemented using an existing CL option.Chad Rosier2012-11-092-10/+5
| | | | llvm-svn: 167622
* Add support for -mstrict-align compiler option for ARM targets.Chad Rosier2012-11-092-5/+10
| | | | | | rdar://12340498 llvm-svn: 167620
* indentNadav Rotem2012-11-091-2/+2
| | | | llvm-svn: 167607
* Recommit modified r167540.Amara Emerson2012-11-081-4/+19
| | | | | | | Improve ARM build attribute emission for architectures types. This also changes the default architecture emitted for a generic CPU to "v7". llvm-svn: 167574
* Add support of RTM from TSX extensionMichael Liao2012-11-0811-46/+159
| | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
* [mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node.Akira Hatanaka2012-11-072-0/+27
| | | | | | Patch by Sasa Stankovic. llvm-svn: 167548
* Delete MipsFunctionInfo::NextStackOffset. No functionality change intended. Akira Hatanaka2012-11-072-10/+6
| | | | llvm-svn: 167546
* Revert r167540 until regression tests are updated.Amara Emerson2012-11-071-21/+4
| | | | llvm-svn: 167545
* Improve ARM build attribute emission for architectures types.Amara Emerson2012-11-071-4/+21
| | | | | | This also changes the default architecture emitted for a generic CPU to "v7". llvm-svn: 167540
* [arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier2012-11-071-1/+4
| | | | | | | classes. For my test case the number of errors drop from 356 to 21. Part of rdar://12594152 llvm-svn: 167508
* Simplify code. No functionality change.Jakub Staszak2012-11-061-1/+1
| | | | llvm-svn: 167505
* Make the helper functions static. No functional change.Nadav Rotem2012-11-061-3/+5
| | | | llvm-svn: 167501
* Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering allChad Rosier2012-11-067-28/+23
| | | | | | | | | | | | registers. Previously, the register we being marked as implicitly defined, but not killed. In some cases this would cause the register scavenger to spill a dead register. Also, use an empty register mask to simplify the logic and to reduce the memory footprint. rdar://12592448 llvm-svn: 167499
* CostModel: add another known vector trunc optimization.Nadav Rotem2012-11-061-0/+1
| | | | llvm-svn: 167488
* Cost Model: add tables for some avx type-conversion hacks.Nadav Rotem2012-11-062-2/+61
| | | | llvm-svn: 167480
* Remove tailing whitespacesMichael Liao2012-11-061-4/+4
| | | | llvm-svn: 167445
* ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.Andrew Trick2012-11-061-2/+1
| | | | | | | This is in preparation for adding "weak" DAG edges, but generally simplifies the design. llvm-svn: 167435
* Refactor the getTypeLegalizationCost interface. No functionality change.Nadav Rotem2012-11-052-24/+17
| | | | llvm-svn: 167422
* CostModel: Add tables for the common x86 compares.Nadav Rotem2012-11-052-8/+83
| | | | llvm-svn: 167421
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