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* This reverts commit r211533 and r211539.Rafael Espindola2014-06-231-54/+1
| | | | | | | | | Revert "Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64" Revert "Fix cmake build." It was missing a file. llvm-svn: 211540
* Fix cmake build.Juergen Ributzka2014-06-231-1/+0
| | | | llvm-svn: 211539
* Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64Weiming Zhao2014-06-232-1/+55
| | | | | | | | | | | | | | | | | | | This patch is based on the changes from ARM target [1,2] Based on ARM doc [3], if the literal value can be loaded with a valid MOV, it can emit that instruction. This is implemented in this patch. [1] Fix PR18345: ldr= pseudo instruction produces incorrect code when using in inline assembly Author: David Peixotto <dpeixott@codeaurora.org> commit b92cca222898d87bbc764fa22e805adb04ef7f13 (r200777) [2] Implement the ldr-pseudo opcode for ARM assembly Author: David Peixotto <dpeixott@codeaurora.org> commit 0fa193b08627927ccaa0804a34d80480894614b8 (r197708) [3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/CJAHAIBC.html Differential Revision: http://reviews.llvm.org/D4163 llvm-svn: 211533
* [Mips] Add a target streamer when creating a null streamer.Rafael Espindola2014-06-233-33/+70
| | | | | | Should fix DebugInfo/global.ll on the mips bot. llvm-svn: 211527
* R600/SI: Verify restrictions on div_scale operands.Matt Arsenault2014-06-231-0/+35
| | | | llvm-svn: 211524
* R600/SI: Fix div_scale intrinsic.Matt Arsenault2014-06-234-4/+62
| | | | | | | The operand that must match one of the others does matter, and implement selecting for it. llvm-svn: 211523
* ARMEB: Vector extend operationsChristian Pirker2014-06-232-20/+150
| | | | | | Reviewed at http://reviews.llvm.org/D4043 llvm-svn: 211520
* R600: Remove AMDILISelLoweringMatt Arsenault2014-06-236-48/+13
| | | | llvm-svn: 211519
* R600: Select is not expensive.Matt Arsenault2014-06-231-0/+7
| | | | llvm-svn: 211518
* R600: Move add/sub with overflow out of AMDILISelLoweringMatt Arsenault2014-06-233-19/+12
| | | | | | Add more tests for these. llvm-svn: 211517
* R600: Move more out of AMDILISelLoweringMatt Arsenault2014-06-233-37/+19
| | | | llvm-svn: 211516
* R600: Don't set fp_round_inreg action.Matt Arsenault2014-06-231-9/+0
| | | | | | | There's no point in setting this since it seems to only by created in 1 place for ppcf128 llvm-svn: 211515
* R600/SI: Handle i64 sub.Matt Arsenault2014-06-234-13/+25
| | | | | | We can handle it the same way as add llvm-svn: 211514
* R600/SI: Move selection of i64 add to separate function.Matt Arsenault2014-06-231-39/+43
| | | | | | Also don't use a SmallVector for fixed size array. llvm-svn: 211513
* R600: Rename AMDIL fileMatt Arsenault2014-06-237-38/+33
| | | | llvm-svn: 211512
* Fix missing words in sentenceMatt Arsenault2014-06-231-3/+3
| | | | llvm-svn: 211511
* Use helper functionMatt Arsenault2014-06-231-7/+2
| | | | llvm-svn: 211510
* Alphabetize forward declarationsMatt Arsenault2014-06-231-2/+2
| | | | llvm-svn: 211509
* [PowerPC] Refactor getMinCallFrameSize / getMinCallArgumentsSizeUlrich Weigand2014-06-234-51/+20
| | | | | | | | | | | | | | | | | | | | As of r211495, the only remaining users of getMinCallFrameSize are in core ABI code (LowerFormalParameter / LowerCall). This is actually a good thing, since the details of the parameter save area are ABI specific. With the new ELFv2 ABI in particular, the rules defining the size of the save area will become significantly more complex, so it wouldn't make sense to implement those outside ABI code that has all required information. In preparation, this patch eliminates the getMinCallFrameSize (and associated getMinCallArgumentsSize) routines, and inlines them into all callers. Note that since nearly all call arguments are constant, this allows simplifying the inlined copies to a single line everywhere. No change in generate code expected. llvm-svn: 211497
* [PowerPC] Allow stack frames without parameter save areaUlrich Weigand2014-06-232-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PPCFrameLowering::determineFrameLayout routine currently ensures that every function that allocates a stack frame provides space for the parameter save area (via PPCFrameLowering::getMinCallFrameSize). This is actually not necessary. There may be functions that never call another routine but still allocate a frame; those do not require the parameter save area. In the future, with the ELFv2 ABI, even some routines that do call other functions do not need to allocate the parameter save area. While it is not a bug to allocate the parameter area when it is not needed, it is better to avoid it to save stack space. Note that when any particular function call requires the parameter save area, this space will already have been included by ABI code in the size the CALLSEQ_START insn is annotated with, and therefore included in the size returned by MFI->getMaxCallFrameSize(). This means that determineFrameLayout simply does not need to care about the parameter save area. (It still needs to ensure that every frame provides the linkage area.) This is implemented by this patch. Note that this exposed a bug in the new fast-isel code where the parameter area was *not* included in the CALLSEQ_START size; this is also fixed. A couple of test cases needed to be adapted for the new (smaller) stack frame size those tests now see. llvm-svn: 211495
* [PowerPC] Fix IsDarwin arg in PPCFrameLowering:: callsUlrich Weigand2014-06-231-5/+5
| | | | | | | | | | | | | | | | As remarked in the commit message to r211493, in several places throughout the 64-bit SVR4 ABI code there are calls to PPCFrameLowering::getLinkageSize and getMinCallFrameSize using an incorrect IsDarwin argument of "true". (Some of those were made explicit by the above refactoring patch, others have been there all along.) This patch fixes those places to pass "false" for IsDarwin. No change in generated code expected. llvm-svn: 211494
* [PowerPC] Refactor setMinReservedArea and CalculateParameterAndLinkageAreaSizeUlrich Weigand2014-06-232-127/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PPCISelLowering.cpp routines PPCTargetLowering::setMinReservedArea and CalculateParameterAndLinkageAreaSize are currently used as subroutines from both 64-bit SVR4 and Darwin ABI code. However, the two ABIs are already quite different w.r.t. AltiVec conventions, and they will become more different when the ELFv2 ABI is supported. Also, in general it seems better to disentangle ABI support routines for different ABIs to avoid accidentally affecting one ABI when intending to change only the other. (Actually, the current code strictly speaking already contains a bug: these routines call PPCFrameLowering::getMinCallFrameSize and PPCFrameLowering::getLinkageSize with the IsDarwin parameter set to "true" even on 64-bit SVR4. This bug currently has no adverse effect since those routines always return the same for 64-bit SVR4 and 64-bit Darwin, but it still seems wrong ... I'll fix this in a follow-up commit shortly.) To remove this code sharing, I'm simply inlining both routines into all call sites (there are just two each, one for 64-bit SVR4 and one for Darwin), and simplifying due to constant parameters where possible. A small piece of code that *does* make sense to share is refactored into the new routine EnsureStackAlignment, now also called from 32-bit SVR4 ABI code. No change in generated code is expected. llvm-svn: 211493
* [PowerPC] Fix on-stack AltiVec arguments with 64-bit SVR4Ulrich Weigand2014-06-231-44/+29
| | | | | | | | | | | | | | | | | | Current 64-bit SVR4 code seems to have some remnants of Darwin code in AltiVec argument handing. This had the effect that AltiVec arguments (or subsequent arguments) were not correctly placed in the parameter area in some cases. The correct behaviour with the 64-bit SVR4 ABI is: - All AltiVec arguments take up space in the parameter area, just like any other arguments, whether vararg or not. - They are always 16-byte aligned, skipping a parameter area doubleword (and the associated GPR, if any), if necessary. This patch implements the correct behaviour and adds a test case. (Verified against GCC behaviour via the ABI compat test suite.) llvm-svn: 211492
* ARM: mark UBFX as not allowing PC.Tim Northover2014-06-231-2/+2
| | | | | | | | | Strictly, it's unpredictable. But we don't quite model that yet and an error is better than ignoring the issue. This one somehow got left out before though. rdar://problem/15997748 llvm-svn: 211490
* Revert r211399, "Generate native unwind info on Win64"NAKAMURA Takumi2014-06-226-325/+117
| | | | | | It broke Legacy JIT Tests on x86_64-{mingw32|msvc}, aka Windows x64. llvm-svn: 211480
* R600: Use LowerSDIVREM for i64 node replaceJan Vesely2014-06-223-92/+120
| | | | | | | | v2: move div/rem node replacement to R600ISelLowering make lowerSDIVREM protected Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211478
* R600: Implement custom SDIVREM.Jan Vesely2014-06-222-4/+44
| | | | | | | | | | Instead of separate SDIV/SREM. SDIV used UDIV which in turn used UDIVREM anyway. SREM used SDIV(UDIV->UDIVREM)+MUL+SUB, using UDIVREM directly is more efficient. v2: Don't use all caps names Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211477
* Fix PR20087 by using the source index when changing the vector loadFilipe Cabecinhas2014-06-221-2/+2
| | | | llvm-svn: 211472
* [X86] Add ISel patterns to select SSE3/AVX ADDSUB instructions.Andrea Di Biagio2014-06-211-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds ISel patterns to select SSE3/AVX ADDSUB instructions from a sequence of "vadd + vsub + blend". Example: /// typedef float float4 __attribute__((ext_vector_type(4))); float4 foo(float4 A, float4 B) { float4 X = A - B; float4 Y = A + B; return (float4){X[0], Y[1], X[2], Y[3]}; } /// Before this patch, (with flag -mcpu=corei7) llc produced the following assembly sequence: movaps %xmm0, %xmm2 addps %xmm1, %xmm2 subps %xmm1, %xmm0 blendps $10, %xmm2, %xmm0 With this patch, we now get a single addsubps %xmm1, %xmm0 llvm-svn: 211427
* Delete dead code.Rafael Espindola2014-06-201-17/+8
| | | | | | The compact unwind info is only used by code that knows it is supported. llvm-svn: 211412
* Don't produce eh_frame relocations when targeting the IOS simulator.Rafael Espindola2014-06-201-2/+3
| | | | | | First step for fixing pr19185. llvm-svn: 211404
* Generate native unwind info on Win64Reid Kleckner2014-06-206-117/+325
| | | | | | | | | | | | | | | | | | | | This patch enables LLVM to emit Win64-native unwind info rather than DWARF CFI. It handles all corner cases (I hope), including stack realignment. Because the unwind info is not flexible enough to describe stack frames with a gap of unknown size in the middle, such as the one caused by stack realignment, I modified register spilling code to place all spills into the fixed frame slots, so that they can be accessed relative to the frame pointer. Patch by Vadim Chugunov! Reviewed By: rnk Differential Revision: http://reviews.llvm.org/D4081 llvm-svn: 211399
* R600/SI: Add patterns for ctpop inside a branchTom Stellard2014-06-201-12/+38
| | | | llvm-svn: 211378
* R600/SI: Add a pattern for f32 ftruncTom Stellard2014-06-203-5/+4
| | | | llvm-svn: 211377
* R600: Expand vector flog2Tom Stellard2014-06-201-0/+1
| | | | llvm-svn: 211376
* R600: Expand vector fexp2Tom Stellard2014-06-201-0/+1
| | | | llvm-svn: 211375
* R600/SI: SI Control Flow Annotation bug fixedTom Stellard2014-06-201-25/+21
| | | | | | | | | | | | Mixing of AddAvailableValue and GetValueAtEndOfBlock methods of SSAUpdater leaded to the endless loop generation when the nested loops annotated. This fixes a bug in the OCL_ML/KNN OpenCV test. The test case is too complex for FileCheck and would be very fragile. Patch by: Elena Denisova llvm-svn: 211374
* R600/SI: Add a VALU pattern for i64 xorTom Stellard2014-06-201-4/+7
| | | | llvm-svn: 211373
* [PowerPC] Fix small argument stack slot offset for LEUlrich Weigand2014-06-201-11/+20
| | | | | | | | | | | | | | When small arguments (structures < 8 bytes or "float") are passed in a stack slot in the ppc64 SVR4 ABI, they must reside in the least significant part of that slot. On BE, this means that an offset needs to be added to the stack address of the parameter, but on LE, the least significant part of the slot has the same address as the slot itself. This changes the PowerPC back-end ABI code to only add the small argument stack slot offset for BE. It also adds test cases to verify the correct behavior on both BE and LE. llvm-svn: 211368
* Allow a target to create a null streamer.Rafael Espindola2014-06-204-71/+41
| | | | | | | | | Targets can assume that a target streamer is present, so they have to be able to construct a null streamer in order to set the target streamer in it to. Fixes a crash when using the null streamer with arm. llvm-svn: 211358
* Emit the ARM build attributes ABI_PCS_wchar_t and ABI_enum_size.Oliver Stannard2014-06-201-0/+26
| | | | | | | Emit the ARM build attributes ABI_PCS_wchar_t and ABI_enum_size based on module flags metadata. llvm-svn: 211349
* ps][mips64r6] Added LSA/DLSA instructionsZoran Jovanovic2014-06-203-2/+35
| | | | | | Differential Revision: http://reviews.llvm.org/D3897 llvm-svn: 211346
* R600: Trivial subtarget feature cleanups.Matt Arsenault2014-06-202-11/+5
| | | | | | | Remove an unused AMDIL leftover, correct extra periods appearing in the help menu. llvm-svn: 211341
* Add Support to Recognize and Vectorize NON SIMD instructions in SLPVectorizer.Karthik Bhat2014-06-202-28/+85
| | | | | | | | | This patch adds support to recognize patterns such as fadd,fsub,fadd,fsub.../add,sub,add,sub... and vectorizes them as vector shuffles if they are profitable. These patterns of vector shuffle can later be converted to instructions such as addsubpd etc on X86. Thanks to Arnold and Hal for the reviews. http://reviews.llvm.org/D4015 llvm-svn: 211339
* [x86] Make the x86 PACKSSWB, PACKSSDW, PACKUSWB, and PACKUSDWChandler Carruth2014-06-204-21/+152
| | | | | | | | | | | | | | | instructions available as synthetic SDNodes PACKSS and PACKUS that will select to the correct instruction variants based on the return type. This allows us to use these rather important instructions when lowering vector shuffles. Also moves the relevant instruction definitions to be split out from the fully generic multiclasses to allow them to match these new SDNodes in the same way that the UNPCK instructions do. No functionality should actually be changed here. llvm-svn: 211332
* Add a new subtarget hook for whether or not we'd like to enableEric Christopher2014-06-194-7/+17
| | | | | | | | | the atomic load linked expander pass to run for a particular subtarget. This requires a check of the subtarget and so save the TargetMachine rather than only TargetLoweringInfo and update all callers. llvm-svn: 211314
* Fix typosAlp Toker2014-06-193-3/+3
| | | | llvm-svn: 211304
* [mips] Implementation of dli.Matheus Almeida2014-06-192-7/+97
| | | | | | | | | | | Patch by David Chisnall His work was sponsored by: DARPA, AFRL Some small modifications to the original patch: we now error if it's not possible to expand an instruction (mips-expansions-bad.s has some examples). Added some comments to the expansions. llvm-svn: 211271
* [mips] Small update to the logic behind the expansion of assembly pseudo ↵Matheus Almeida2014-06-191-9/+20
| | | | | | | | | | | | | | | | instructions. Summary: The functions that do the expansion now return false on success and true otherwise. This is so we can catch some errors during the expansion (e.g.: immediate too large). The next patch adds some test cases. Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4214 llvm-svn: 211269
* [X86] Teach how to combine horizontal binop even in the presence of undefs.Andrea Di Biagio2014-06-191-40/+115
| | | | | | | | | | | | | | Before this change, the backend was unable to fold a build_vector dag node with UNDEF operands into a single horizontal add/sub. This patch teaches how to combine a build_vector with UNDEF operands into a horizontal add/sub when possible. The algorithm conservatively avoids to combine a build_vector with only a single non-UNDEF operand. Added test haddsub-undef.ll to verify that we correctly fold horizontal binop even in the presence of UNDEFs. llvm-svn: 211265
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