summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* AMDGPU: Fix off by one error in register parsingMatt Arsenault2015-11-031-4/+5
| | | | | | If trying to use one past the end, this would assert. llvm-svn: 252008
* Align whitespaceDerek Schuff2015-11-032-4/+4
| | | | llvm-svn: 252003
* [WebAssembly] Support wasm select operatorDerek Schuff2015-11-032-0/+10
| | | | | | | | | | | | | | Summary: Add support for wasm's select operator, and lower LLVM's select DAG node to it. Reviewers: sunfish Subscribers: dschuff, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D14295 llvm-svn: 252002
* AMDGPU: s[102:103] is unavailable on VIMatt Arsenault2015-11-031-1/+10
| | | | llvm-svn: 252000
* AMDGPU: Define correct number of SGPRsMatt Arsenault2015-11-032-6/+10
| | | | | | | | | There are actually 104 so 2 were missing. More assembler tests with high register number tuples will be included in later patches. llvm-svn: 251999
* AMDGPU: Make findUsedSGPR more readableMatt Arsenault2015-11-031-7/+18
| | | | | | Add more comments etc. llvm-svn: 251996
* AMDGPU: Initialize SIFixSGPRCopies so -print-after worksMatt Arsenault2015-11-033-8/+15
| | | | llvm-svn: 251995
* AMDGPU: Alphabetize includesMatt Arsenault2015-11-031-1/+1
| | | | llvm-svn: 251994
* [X86][XOP] Add support for the matching of the VPCMOV bit select instructionSimon Pilgrim2015-11-031-0/+10
| | | | | | | | | | XOP has the VPCMOV instruction that performs the common vector bit select operation OR( AND( SRC1, SRC3 ), AND( SRC2, ~SRC3 ) ) This patch adds tablegen pattern matching for this instruction. Differential Revision: http://reviews.llvm.org/D8841 llvm-svn: 251975
* [X86] Generate .cfi_adjust_cfa_offset correctly when pushing argumentsMichael Kuperstein2015-11-033-27/+64
| | | | | | | | | | | | | | | When push instructions are being used to pass function arguments on the stack, and either EH or debugging are enabled, we need to generate .cfi_adjust_cfa_offset directives appropriately. For (synch) EH, it is enough for the CFA offset to be correct at every call site, while for debugging we want to be correct after every push. Darwin does not support this well, so don't use pushes whenever it would be required. Differential Revision: http://reviews.llvm.org/D13767 llvm-svn: 251904
* AVX512: add encoding tests for vmovq/d instructions.Igor Breger2015-11-031-1/+1
| | | | llvm-svn: 251903
* Fix build problme introduced in r251883Matthias Braun2015-11-031-1/+1
| | | | llvm-svn: 251888
* ScheduleDAGInstrs: Remove IsPostRA flag; NFCMatthias Braun2015-11-031-2/+1
| | | | | | | | | | | | | | | | | ScheduleDAGInstrs doesn't behave differently before or after register allocation. It was only used in a method of MachineSchedulerBase which behaved differently in MachineScheduler/PostMachineScheduler. Change this to let MachineScheduler/PostMachineScheduler just pass in a parameter to that function. The order of the LiveIntervals* and bool RemoveKillFlags paramters have been switched to make out-of-tree code fail instead of unintentionally passing a value intended for the IsPostRA flag to the (previously following and default initialized) RemoveKillFlags. Differential Revision: http://reviews.llvm.org/D14245 llvm-svn: 251883
* [Hexagon] Fixing mistaken case fallthrough.Colin LeMahieu2015-11-031-0/+1
| | | | llvm-svn: 251867
* AMDGPU: Stop assuming vreg for build_vectorMatt Arsenault2015-11-022-20/+40
| | | | | | | | | | | | | This was causing a variety of test failures when v2i64 is added as a legal type. SIFixSGPRCopies should correctly handle the case of vector inputs to a scalar reg_sequence, so this isn't necessary anymore. This was hiding some deficiencies in how reg_sequence is handled later, but this shouldn't be a problem anymore since the register class copy of a reg_sequence is now done before the reg_sequence. llvm-svn: 251860
* [WebAssembly] Make WebAssemblyCodeGen depend on WebAssemblyAsmPrinterDerek Schuff2015-11-021-1/+1
| | | | llvm-svn: 251859
* AMDGPU: Error on graphics shaders with HSAMatt Arsenault2015-11-021-0/+8
| | | | | | | | I've found myself pointlessly debugging problems from running graphics tests with an HSA triple a few times, so stop this from happening again. llvm-svn: 251858
* AMDGPU: Distribute SGPR->VGPR copies of REG_SEQUENCEMatt Arsenault2015-11-021-23/+89
| | | | | | | Make the REG_SEQUENCE be a VGPR, and do the register class copy first. llvm-svn: 251855
* [PPC64LE] Properly initialize instr-info in PPCVSXSwapRemoval passBill Schmidt2015-11-021-1/+1
| | | | | | | | Replace some hacky code with the proper way to get at this data. No functional change. llvm-svn: 251848
* WatchOS: update default CPU for triple after t2dsp -> dsp renameTim Northover2015-11-021-2/+2
| | | | llvm-svn: 251814
* Fix for bootstrap bug introduced in r244921Nemanja Ivanovic2015-11-022-3/+2
| | | | | | | | | | This revision has introduced an issue that only affects bootstrapped compiler when it is printing the ASM. It turns out that the new code path taken due to legalizing a scalar_to_vector of i64 -> v2i64 exposes a missing check in a micro optimization to change a load followed by a scalar_to_vector into a load and splat instruction on PPC. llvm-svn: 251798
* AVX512: Implemented encoding and intrinsics for VBROADCASTI32x2 and ↵Igor Breger2015-11-023-0/+54
| | | | | | | | VBROADCASTF32x2 instructions. Differential Revision: http://reviews.llvm.org/D14216 llvm-svn: 251781
* [X86] Remove assertions that check for valid scale values on scatter/gather ↵Craig Topper2015-11-021-8/+0
| | | | | | intrinsics. Nothing upstream prevented illegal values from getting here. llvm-svn: 251780
* [X86] Fold 'if' followed by just an llvm_unreachable into an assert.Craig Topper2015-11-021-8/+7
| | | | llvm-svn: 251778
* [X86] Use isa instead of dyn_cast in a bool context. NFCCraig Topper2015-11-021-2/+2
| | | | llvm-svn: 251777
* [X86] Remove some llvm_unreachables after switches that already have an ↵Craig Topper2015-11-021-5/+3
| | | | | | unreachable in their default case. llvm-svn: 251776
* [X86] Remove a 'break' after an llvm_unreachable.Craig Topper2015-11-021-3/+1
| | | | llvm-svn: 251775
* [X86] Use cast instead of dyn_cast and a null check marked unreachable.Craig Topper2015-11-021-8/+3
| | | | llvm-svn: 251774
* [X86] Use MVT instead of EVT when the type is known to be simple. NFCCraig Topper2015-11-022-89/+80
| | | | llvm-svn: 251772
* Untabify.NAKAMURA Takumi2015-11-023-7/+7
| | | | llvm-svn: 251769
* AVX-512: Optimized SIMD truncate operations for AVX512F set.Elena Demikhovsky2015-11-012-3/+23
| | | | | | | | | | | | Optimized <8 x i32> to <8 x i16> <4 x i64> to < 4 x i32> <16 x i16> to <16 x i8> All these oprtrations use now AVX512F set (KNL). Before this change it was implemented with AVX2 set. Differential Revision: http://reviews.llvm.org/D14108 llvm-svn: 251764
* [X86] Replace getScalarType with getVectorElementType when the type is ↵Craig Topper2015-10-311-29/+29
| | | | | | already known to be a vector. This should result in slightly less code. NFC llvm-svn: 251751
* [X86] Convert to MVT instead of calling EVT functions since we already know ↵Craig Topper2015-10-311-2/+2
| | | | | | the type is simple. NFC llvm-svn: 251745
* [X86] Call getScalarSizeInBits() instead of ↵Craig Topper2015-10-311-5/+5
| | | | | | getScalarType().getScalarSizeInBits(). NFC llvm-svn: 251744
* [X86] Remove two const references to the return value of a constructor and ↵Craig Topper2015-10-311-2/+2
| | | | | | just use normal object creation syntax. NFC llvm-svn: 251743
* [X86] Replace EVT with MVT in some more places. NFCCraig Topper2015-10-311-12/+12
| | | | llvm-svn: 251742
* [X86] Fix indentation of case statements in switch. NFCCraig Topper2015-10-311-16/+16
| | | | llvm-svn: 251741
* [X86] Reduce math for index calculation for inserting and extracting ↵Craig Topper2015-10-311-14/+16
| | | | | | subvectors and elements by exploiting the fact that all supported vector types have a power 2 number of elements. llvm-svn: 251740
* [WebAssembly] Fix import statementJF Bastien2015-10-301-9/+10
| | | | | | | | | | Summary: Imports should be generated like (param i32 f32...) not (param i32) (param f32) ... Author: binji Reviewers: jfb Subscribers: jfb, dschuff llvm-svn: 251714
* [X86] Use is128BitVector/is256BitVector/is512BitVector in place of ↵Craig Topper2015-10-301-17/+16
| | | | | | getSizeInBits == in some places. NFC llvm-svn: 251687
* [X86] Minor formatting fixes. NFC.Craig Topper2015-10-301-9/+8
| | | | llvm-svn: 251686
* [X86] Use MVT instead of EVT in some places. NFCCraig Topper2015-10-301-37/+41
| | | | | | Prior to this the compiled code probably had extra checks for extended types that won't ever execute. llvm-svn: 251682
* [X86][SSE] Shuffle blends with zeroSimon Pilgrim2015-10-291-19/+49
| | | | | | | | This patch generalizes the zeroing of vector elements with the BLEND instructions. Currently a zero vector will only blend if the shuffled elements are correctly inline, this patch recognises when a vector input is zero (or zeroable) and modifies a local copy of the shuffle mask to support a blend. As a zeroable vector input may not be all zeroes, the zeroable vector is regenerated if necessary. Differential Revision: http://reviews.llvm.org/D14050 llvm-svn: 251659
* [SystemZ] Make the CCRegs regclass non-allocatable.Jonas Paulsson2015-10-293-4/+6
| | | | | | | | | | | | | | | | | | | | | This was discovered to be necessary while running memchr-01.ll with -verify-machinstrs, because it is not allowed to have a phys reg live accross block boundaries while on SSA form, if the register is allocatable (expect in entry block and landing pads). In this test case, stringRRE pseudos are expanded after isel by adding a loop block which produces a live out CC register. To make the test pass, it was also necessary to not say that StringRRELoop pseudo uses R0L, this is only true for the StringRRE opcode. -verify-machineinstrs added to memchr-01.ll test. New test case int-cmp-51.ll to test that MachineCSE can eliminate an identical compare (which it couldn't do before). Reviewed by Ulrich Weigand llvm-svn: 251634
* AMDGPU/SI: handle undef for llvm.SI.packf16Marek Olsak2015-10-291-0/+4
| | | | llvm-svn: 251632
* AMDGPU/SI: use S_OR for fneg (fabs f32)Marek Olsak2015-10-291-2/+1
| | | | llvm-svn: 251631
* AMDGPU/SI: use S_AND for i1 truncMarek Olsak2015-10-291-2/+2
| | | | llvm-svn: 251630
* [mips] wrong opcode for ll/sc instructions on mipsr6 when -integrated-as is usedZoran Jovanovic2015-10-291-5/+10
| | | | | | | | | | | | | | | Summary: This commit resolves wrong opcodes for ll and sc instructions for r6 architecutres, which were generated in method MipsTargetLowering::emitAtomicBinary. Author: Jelena.Losic Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D13593 llvm-svn: 251629
* Recognize that ARM1176JZ[F]-S support TrustZoneArtyom Skrobov2015-10-292-1/+4
| | | | | | | | | | | | | | Summary: ARMv6KZ cores were set up incorrectly in ARM.td; also, the SMI mnemonic (the old name for SMC, as defined in ARMv6KZ) wasn't supported. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14154 llvm-svn: 251627
* [mips] Check the register class before replacing materializations of zero ↵Vasileios Kalintiris2015-10-291-0/+5
| | | | | | | | | | | | | | | | | | | | | | with $zero in microMIPS. Summary: The microMIPS register class GPRMM16 does not contain the $zero register. However, MipsSEDAGToDAGISel::replaceUsesWithZeroReg() would replace uses of the $dst register: [d]addiu, $dst, $zero, 0 with the $zero register, without checking for membership in the register class of the target machine operand. Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13984 llvm-svn: 251622
OpenPOWER on IntegriCloud