summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* Add HLE target featureMichael Liao2013-03-264-1/+14
| | | | llvm-svn: 178082
* Enable SandyBridgeModel for all modern Intel P6 descendants.Jakob Stoklund Olesen2013-03-262-34/+44
| | | | | | | | | | | | All Intel CPUs since Yonah look a lot alike, at least at the granularity of the scheduling models. We can add more accurate models for processors that aren't Sandy Bridge if required. Haswell will probably need its own. The Atom processor and anything based on NetBurst is completely different. So are the non-Intel chips. llvm-svn: 178080
* Restore real bit lengths on PPC register numbersHal Finkel2013-03-261-12/+12
| | | | | | | | | | As suggested by Bill Schmidt (in reviewing r178067), use the real register number bit lengths (which is self-documenting, and prevents using illegal numbers), and set only the relevant bits in HWEncoding (which defaults to 0). No functionality change intended. llvm-svn: 178077
* PPC: Use HWEncoding and TRI->getEncodingValueHal Finkel2013-03-268-100/+31
| | | | | | | | | | | As pointed out by Jakob, we don't need to maintain a separate register-numbering table. Instead we should let TableGen generate the table for us from the information (already present) in PPCRegisterInfo.td. TRI->getEncodingValue is now used to access register-encoding values. No functionality change intended. llvm-svn: 178067
* R600/SIMCCodeEmitter.cpp: Prune a couple of unused members, STI and Ctx. ↵NAKAMURA Takumi2013-03-261-3/+1
| | | | | | [-Wunused-private-field] llvm-svn: 178065
* Use multiple virtual registers in PPC CR spillingHal Finkel2013-03-262-25/+35
| | | | | | | | | | | | Now that the register scavenger can support multiple spill slots, and PEI can use virtual-register-based scavenging for multiple simultaneous registers, we can use a virtual register for the transfer register in the CR spilling code. This should eliminate the last place (outside of the prologue/epilogue) where we depend on the unconditional availability of the r0 register. We will soon be able to allocate it (in a somewhat restricted sense) as a GPR. llvm-svn: 178060
* Update PPCRegisterInfo's use of virtual registers to be SSAHal Finkel2013-03-261-3/+5
| | | | | | | | | | | PPC's use of PEI's virtual-register-based scavenging functionality had redefined the virtual registers (it was non-SSA). Now that PEI supports dealing with instructions with multiple virtual registers, this can be cleanup up to use multiple virtual registers and keep SSA form. No functionality change intended. llvm-svn: 178059
* Annotate the remaining x86 instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-263-10/+10
| | | | | | | | | | Now all x86 instructions that have itinerary classes also have SchedRW lists. This is required before the new scheduling models can be used. There are still unannotated instructions remaining, but they don't have itinerary classes either. llvm-svn: 178051
* Annotate x87 and mmx instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-262-31/+71
| | | | | | | This only covers the instructions that were given itinerary classes for the Atom model. llvm-svn: 178050
* Annotate control instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-261-28/+41
| | | | | | | This could definitely be more granular. I am not sure if it makes a difference. llvm-svn: 178049
* Annotate the rest of X86InstrInfo.td with SchedRW lists.Jakob Stoklund Olesen2013-03-261-27/+43
| | | | llvm-svn: 178048
* Add PREFETCHW codegen supportMichael Liao2013-03-265-5/+21
| | | | | | - Add 'PRFCHW' feature defined in AVX2 ISA extension llvm-svn: 178040
* Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.Jyotsna Verma2013-03-262-186/+48
| | | | llvm-svn: 178032
* Hexagon: Remove HexagonMCInst.h file. It has been replaced with ↵Jyotsna Verma2013-03-261-41/+0
| | | | | | MCTargetDesc/HexagonMCInst.h. llvm-svn: 178030
* Revert ARM Scheduler Model: Add resources instructions, map resourcesArnold Schwaighofer2013-03-264-70/+24
| | | | | | | | | | | | | This reverts commit r177968. It is causing failures in a local build bot. "fatal error: error in backend: Expected a variant SchedClass" Original commit message: Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. llvm-svn: 178028
* Remove default case from fully covered switch.Benjamin Kramer2013-03-261-1/+1
| | | | llvm-svn: 178025
* R600/SI: improve post ISel foldingChristian Konig2013-03-261-31/+43
| | | | | | | Not only fold immediates, but avoid unnecessary copies as well. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178024
* R600/SI: improve vector interpolationChristian Konig2013-03-261-0/+20
| | | | | | | Prevent loading M0 multiple times. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178023
* R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLEChristian Konig2013-03-262-14/+8
| | | | | | | Just define the address as unknown instead of VReg_32. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178022
* R600/SI: switch back to RegPressure schedulingChristian Konig2013-03-263-1/+9
| | | | | Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178021
* R600/SI: mark most intrinsics as readnone v2Christian Konig2013-03-261-5/+5
| | | | | | | | | They read from constant register space anyway. v2: fix lit tests Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178020
* R600/SI: replace WQM intrinsicChristian Konig2013-03-265-28/+14
| | | | | | | Just enable WQM when we see an LDS interpolation instruction. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178019
* R600/SI: fix ELSE pseudo op handlingChristian Konig2013-03-261-1/+2
| | | | | | | | | | | Restore the EXEC mask early, otherwise a copy might end up not beeing executed. Candidate for the mesa stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178018
* Patch by Gordon Keiser!Joe Abbey2013-03-261-1/+1
| | | | | | | | | | If PC or SP is the destination, the disassembler erroneously failed with the invalid encoding, despite the manual saying that both are fine. This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a postindexed load, where the offset 0xc is applied to SP after the load occurs. llvm-svn: 178017
* PowerPC: Mark patterns as isCodeGenOnly.Ulrich Weigand2013-03-264-7/+21
| | | | | | | | | | | There remain a number of patterns that cannot (and should not) be handled by the asm parser, in particular all the Pseudo patterns. This commit marks those patterns as isCodeGenOnly. No change in generated code. llvm-svn: 178008
* PowerPC: Simplify handling of fixups.Ulrich Weigand2013-03-264-70/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MCTargetDesc/PPCMCCodeEmitter.cpp current has code like: if (isSVR4ABI() && is64BitMode()) Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_toc16)); else Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_lo16)); This is a problem for the asm parser, since it requires knowledge of the ABI / 64-bit mode to be set up. However, more fundamentally, at this point we shouldn't make such distinctions anyway; in an assembler file, it always ought to be possible to e.g. generate TOC relocations even when the main ABI is one that doesn't use TOC. Fortunately, this is actually completely unnecessary; that code was added to decide whether to generate TOC relocations, but that information is in fact already encoded in the VariantKind of the underlying symbol. This commit therefore merges those fixup types into one, and then decides which relocation to use based on the VariantKind. No changes in generated code. llvm-svn: 178007
* PowerPC: Simplify FADD in round-to-zero mode.Ulrich Weigand2013-03-264-101/+50
| | | | | | | | | | | | | | | | | | | | | | | As part of the the sequence generated to implement long double -> int conversions, we need to perform an FADD in round-to-zero mode. This is problematical since the FPSCR is not at all modeled at the SelectionDAG level, and thus there is a risk of getting floating point instructions generated out of sequence with the instructions to modify FPSCR. The current code handles this by somewhat "special" patterns that in part have dummy operands, and/or duplicate existing instructions, making them awkward to handle in the asm parser. This commit changes this by leaving the "FADD in round-to-zero mode" as an atomic operation on the SelectionDAG level, and only split it up into real instructions at the MI level (via custom inserter). Since at *this* level the FPSCR *is* modeled (via the "RM" hard register), much of the "special" stuff can just go away, and the resulting patterns can be used by the asm parser. No significant change in generated code expected. llvm-svn: 178006
* PowerPC: Remove LDrs pattern.Ulrich Weigand2013-03-263-16/+9
| | | | | | | | | | | | | | | | | | | | The LDrs pattern is a duplicate of LD, except that it accepts memory addresses where the displacement is a symbolLo64. An operand type "memrs" is defined for just that purpose. However, this wouldn't be necessary if the default "memrix" operand type were to simply accept 64-bit symbolic addresses directly. The only problem with that is that it uses "symbolLo", which is hardcoded to 32-bit. To fix this, this commit changes "memri" and "memrix" to use new operand types for the memory displacement, which allow iPTR instead of i32. This will also make address parsing easier to implment in the asm parser. No change in generated code. llvm-svn: 178005
* PowerPC: Remove ADDIL patterns.Ulrich Weigand2013-03-264-20/+13
| | | | | | | | | | | | | | The ADDI/ADDI8 patterns are currently duplicated into ADDIL/ADDI8L, which describe the same instruction, except that they accept a symbolLo[64] operand instead of a s16imm[64] operand. This duplication confuses the asm parser, and it actually not really needed, since symbolLo[64] already accepts immediate operands anyway. So this commit removes the duplicate patterns. No change in generated code. llvm-svn: 178004
* PowerPC: Use CCBITRC operand for ISEL patterns.Ulrich Weigand2013-03-265-46/+19
| | | | | | | | | | | | This commit changes the ISEL patterns to use a CCBITRC operand instead of a "pred" operand. This matches the actual instruction text more directly, and simplifies use of ISEL with the asm parser. In addition, this change allows some simplification of handling the "pred" operand, as this is now only used by BCC. No change in generated code. llvm-svn: 178003
* PowerPC: Simplify BLR pattern.Ulrich Weigand2013-03-263-12/+6
| | | | | | | | | | | | | | | | | The BLR pattern cannot be recognized by the asm parser in its current form. This complexity is due to an apparent attempt to enable conditional BLR variants. However, none of those can ever be generated by current code; the pattern is only ever created using the default "pred" operand. To simplify the pattern and allow it to be recognized by the parser, this commit removes those attempts at conditional BLR support. When we later come back to actually add real conditional BLR, this should probably be done via a fully generic conditional branch pattern. No change in generated code. llvm-svn: 178002
* PowerPC: Move some 64-bit branch patterns.Ulrich Weigand2013-03-261-17/+18
| | | | | | | | | | | | In PPCInstr64Bit.td, some branch patterns appear in a different sequence than the corresponding 32-bit patterns in PPCInstrInfo.td. To simplify future changes that affect both files, this commit moves those patterns to rearrange them into a similar sequence. No effect on generated code. llvm-svn: 178001
* R600: fix DenseMap with pointer key iteration in the structurizerChristian Konig2013-03-261-2/+4
| | | | | | | | | Use a MapVector on types where the iteration order matters. Otherwise we doesn't always produce a deterministic output. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 177999
* ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer2013-03-264-24/+70
| | | | | | | | Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. llvm-svn: 177968
* ARM Scheduler Model: Partial implementation of the new machine scheduler modelArnold Schwaighofer2013-03-261-0/+57
| | | | | | | | | | This is very much work in progress. Please send me a note if you start to depend on the added abstract read/write resources. They are subject to change until further notice. The old itinerary is still the default. llvm-svn: 177967
* Revise alignment checking/calculation on 256-bit unaligned memory accessMichael Liao2013-03-251-7/+6
| | | | | | | | | - It's still considered aligned when the specified alignment is larger than the natural alignment; - The new alignment for the high 128-bit vector should be min(16, alignment) as the pointer is advanced by 16, a power-of-2 offset. llvm-svn: 177947
* Add a scheduling model for Intel Sandy Bridge microarchitecture.Jakob Stoklund Olesen2013-03-251-0/+123
| | | | | | | The model isn't hooked up by this patch because the instruction set isn't fully annotated yet. llvm-svn: 177942
* Remove IIC_DEFAULT from X86Schedule.tdJakob Stoklund Olesen2013-03-255-78/+76
| | | | | | | | All the instructions tagged with IIC_DEFAULT had nothing in common, and we already have a NoItineraries class to represent untagged instructions. llvm-svn: 177937
* Annotate X86InstrCompiler.td with SchedRW lists.Jakob Stoklund Olesen2013-03-251-10/+20
| | | | llvm-svn: 177936
* Annotate shifts and rotates with SchedRW lists.Jakob Stoklund Olesen2013-03-251-17/+37
| | | | llvm-svn: 177935
* X86DisassemblerDecoder.c: Make this C89-compliant.NAKAMURA Takumi2013-03-251-1/+1
| | | | llvm-svn: 177910
* Whitespace.NAKAMURA Takumi2013-03-251-160/+160
| | | | llvm-svn: 177909
* Fix comment.Akira Hatanaka2013-03-251-3/+3
| | | | llvm-svn: 177899
* Use direct types in PowerPC instruction patterns.Ulrich Weigand2013-03-252-270/+262
| | | | | | | | | | This commit updates the PowerPC back-end (PPCInstrInfo.td and PPCInstr64Bit.td) to use types instead of register classes in instruction patterns, along the lines of Jakob Stoklund Olesen's changes in r177835 for Sparc. llvm-svn: 177890
* Use direct types in PowerPC Pat patterns.Ulrich Weigand2013-03-252-113/+113
| | | | | | | | | This commit updates the PowerPC back-end (PPCInstrInfo.td and PPCInstr64Bit.td) to use types instead of register classes in Pat patterns, along the lines of Jakob Stoklund Olesen's changes in r177829 for Sparc. llvm-svn: 177889
* x86 -- add the XTEST instructionDave Zarzycki2013-03-254-31/+30
| | | | llvm-svn: 177888
* x86 -- disassemble the REP/REPNE prefix when neededDave Zarzycki2013-03-251-7/+20
| | | | | | This fixes Apple bug: 13493622 llvm-svn: 177887
* Remove assert. There may be target-dependent attributes left.Bill Wendling2013-03-251-1/+0
| | | | llvm-svn: 177878
* [arm load/store optimizer] When trying to merge a base update load/store, makeChad Rosier2013-03-251-1/+1
| | | | | | | | | | | sure the base register and would-be writeback register don't conflict for stores. This was already being done for loads. Unfortunately, it is rather difficult to create a test case for this issue. It was exposed in 450.soplex at LTO and requires unlucky register allocation. <rdar://13394908> llvm-svn: 177874
* [NVPTX] Fix handling of vector argumentsJustin Holewinski2013-03-242-7/+56
| | | | llvm-svn: 177847
OpenPOWER on IntegriCloud