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* Correct decoder for T1 conditional B encodingRichard Barton2012-06-061-2/+2
| | | | llvm-svn: 158055
* Mark several instructions SSE2 instead of SSE3 as they should be.Craig Topper2012-06-062-9/+11
| | | | llvm-svn: 158049
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-053-19/+126
| | | | | | | Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. llvm-svn: 158021
* Fix header file include order in NVPTX backend NV_CONTRIBYuan Lin2012-06-051-2/+2
| | | | llvm-svn: 158013
* PPC32 uses R2 as the TLS register. Fix the copy and paste.Roman Divacky2012-06-051-3/+3
| | | | llvm-svn: 158004
* X86 itinerary properties.Andrew Trick2012-06-052-2/+29
| | | | llvm-svn: 157981
* ARM itinerary properties.Andrew Trick2012-06-053-22/+10
| | | | llvm-svn: 157980
* misched: Added MultiIssueItineraries.Andrew Trick2012-06-055-15/+13
| | | | | | | | This allows a subtarget to explicitly specify the issue width and other properties without providing pipeline stage details for every instruction. llvm-svn: 157979
* whitespaceAndrew Trick2012-06-052-5/+2
| | | | llvm-svn: 157976
* Revert commit r157966Joel Jones2012-06-051-24/+0
| | | | llvm-svn: 157972
* This change handles a another case for generating the bic instruction Joel Jones2012-06-041-0/+24
| | | | | | | | | when a compile time constant is known. This occurs when implicitly zero extending function arguments from 16 bits to 32 bits. <rdar://problem/11481151> llvm-svn: 157966
* Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node isAkira Hatanaka2012-06-041-1/+2
| | | | | | inserted after the shift-left-logical node. llvm-svn: 157937
* Implement local-exec TLS on PowerPC.Roman Divacky2012-06-046-11/+69
| | | | llvm-svn: 157935
* MIPS TLS: use the model selected by TargetMachine::getTLSModel().Hans Wennborg2012-06-041-3/+4
| | | | | | This was mostly done already in r156162, but I missed one place. llvm-svn: 157929
* Better comments for TLS-related X86 MachineOperand flags.Hans Wennborg2012-06-041-9/+18
| | | | llvm-svn: 157920
* Add intrinsic forms for FMA instructions to opcode folding tables.Craig Topper2012-06-042-109/+141
| | | | llvm-svn: 157917
* Add VFMADDSUB and VFMSUBADD FMA instructions to folding tables. Also add 213 ↵Craig Topper2012-06-041-0/+34
| | | | | | forms of scalar FMA instructions. llvm-svn: 157914
* Fix a copy-and-paste duplication error in the PPC 440 and A2 schedules (no ↵Hal Finkel2012-06-042-42/+0
| | | | | | functionality change). llvm-svn: 157912
* Enable generating PPC pre-increment (r+imm) instructions by default.Hal Finkel2012-06-041-5/+3
| | | | | | | It seems that this no longer causes test suite failures on PPC64 (after r157159), and often gives a performance benefit, so it can be enabled by default. llvm-svn: 157911
* Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.Craig Topper2012-06-035-10/+10
| | | | llvm-svn: 157903
* Rename fma4 intrinsics to just fma since they are now used for both FMA4 and ↵Craig Topper2012-06-031-54/+54
| | | | | | FMA3. Autoupgrade support coming in a separate commit. llvm-svn: 157898
* Revert r157831Manman Ren2012-06-033-331/+0
| | | | llvm-svn: 157896
* Use sse_load_f32/64 for scalar FMA3 intrinsic patterns instead of 128-bit ↵Craig Topper2012-06-031-36/+30
| | | | | | loads to match instruction behavior. llvm-svn: 157895
* Add neverHasSideEffects and mayLoad to FMA3 instructions.Craig Topper2012-06-031-0/+5
| | | | llvm-svn: 157894
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-0215-22/+22
| | | | llvm-svn: 157885
* remove an unused variable.Chris Lattner2012-06-021-1/+1
| | | | llvm-svn: 157872
* Remove code which is no longer needed in MipsAsmPrinter and MipsMCInstLower.Akira Hatanaka2012-06-023-171/+0
| | | | llvm-svn: 157867
* Set operation actions for load/store nodes in the Mips backend.Akira Hatanaka2012-06-021-0/+11
| | | | llvm-svn: 157866
* Add definitions of 32/64-bit unaligned load/store instructions for Mips.Akira Hatanaka2012-06-022-27/+70
| | | | llvm-svn: 157865
* Define functions MipsTargetLowering::LowerLOAD and LowerSTORE whichAkira Hatanaka2012-06-022-0/+140
| | | | | | custom-lower unaligned load and store nodes. llvm-svn: 157864
* Define Mips specific unaligned load/store nodes.Akira Hatanaka2012-06-023-1/+40
| | | | llvm-svn: 157863
* Expand unaligned i16 loads/stores for the Mips backend.Akira Hatanaka2012-06-021-1/+0
| | | | | | | | This is the first of a series of patches which make changes to the backend to emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction selection. llvm-svn: 157862
* In MipsMCInstLower::LowerSymbolOperand, get offset from symbol ifAkira Hatanaka2012-06-021-2/+4
| | | | | | the MachineOperand type has a valid offset. llvm-svn: 157861
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-013-11/+8
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* [arm-fast-isel] Fix handling of the frameaddress intrinsic. If depth is 0Chad Rosier2012-06-011-1/+1
| | | | | | then DestReg is undefined. llvm-svn: 157840
* Switch some getAliasSet clients to MCRegAliasIterator.Jakob Stoklund Olesen2012-06-013-19/+10
| | | | | | | MCRegAliasIterator can optionally visit the register itself, allowing for simpler code. llvm-svn: 157837
* X86: peephole optimization to remove cmp instructionManman Ren2012-06-013-0/+331
| | | | | | | | | | | | | | | This patch will optimize the following: sub r1, r3 cmp r3, r1 or cmp r1, r3 bge L1 TO sub r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can eliminate the "cmp" instruction. llvm-svn: 157831
* ARM: properly handle alignment for struct byval.Manman Ren2012-06-013-250/+275
| | | | | | | | | Factor out the expansion code into a function. This change is to be enabled in clang. rdar://9877866 llvm-svn: 157830
* Implement the local-dynamic TLS model for x86 (PR3985)Hans Wennborg2012-06-0111-17/+274
| | | | | | | | | This implements codegen support for accesses to thread-local variables using the local-dynamic model, and adds a clean-up pass so that the base address for the TLS block can be re-used between local-dynamic access on an execution path. llvm-svn: 157818
* Enable automatic detection of FMA3 support to allow intrinsics to be used.Craig Topper2012-06-011-6/+4
| | | | llvm-svn: 157805
* Remove fadd(fmul) patterns for FMA3. This needs to be implemented by paying ↵Craig Topper2012-06-011-212/+0
| | | | | | attention to FP_CONTRACT and matching @llvm.fma which is not available yet. This will allow us to enablle intrinsic use at least though. llvm-svn: 157804
* Add VFNSUB* instructions to folding table.Craig Topper2012-06-011-0/+17
| | | | llvm-svn: 157802
* Remove a trailing space and fix a comment.Craig Topper2012-06-011-3/+2
| | | | llvm-svn: 157801
* Tidy up. Remove trailing spaces and fix the worst of the 80 column violations.Craig Topper2012-06-011-74/+90
| | | | llvm-svn: 157799
* ARM: support struct byval in llvmManman Ren2012-06-013-15/+279
| | | | | | | | | | We handle struct byval by inserting a pseudo op, which will be expanded to a loop at ExpandISelPseudos. A separate patch for clang will be submitted to enable struct byval. rdar://9877866 llvm-svn: 157793
* Put the shiny new MCSubRegIterator to work.Chad Rosier2012-06-011-8/+6
| | | | llvm-svn: 157783
* Add support for return value promotion in X86 calling conventions.Jakob Stoklund Olesen2012-05-311-0/+10
| | | | | | Patch by Yiannis Tsiouris! llvm-svn: 157757
* X86: replace SUB with CMP if possibleManman Ren2012-05-312-0/+41
| | | | | | | | | | | | | | | | | This patch will optimize the following movq %rdi, %rax subq %rsi, %rax cmovsq %rsi, %rdi movq %rdi, %rax to cmpq %rsi, %rdi cmovsq %rsi, %rdi movq %rdi, %rax Perform this optimization if the actual result of SUB is not used. rdar: 11540023 llvm-svn: 157755
* Add a PrintRegUnit helper similar to PrintReg.Jakob Stoklund Olesen2012-05-311-0/+21
| | | | | | | | | | | Reg-units are named after their root registers, and most units have a single root, so they simply print as 'AL', 'XMM0', etc. The rare dual root reg-units print as FPSCR~FPSCR_NZCV, FP0~ST7, ... The printing piggybacks on the existing register name tables, so no extra const data space is required. llvm-svn: 157754
* Fix typosJoel Jones2012-05-311-2/+2
| | | | llvm-svn: 157752
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