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* Add LLVM support for remaining integer divide and permute instructions from ↵Nemanja Ivanovic2015-04-096-52/+133
| | | | | | | | | | | ISA 2.06 This is the patch corresponding to review: http://reviews.llvm.org/D8406 It adds some missing instructions from ISA 2.06 to the PPC back end. llvm-svn: 234546
* Simplify use of formatted_raw_ostream.Rafael Espindola2015-04-093-12/+14
| | | | | | | | | | | | | | | formatted_raw_ostream is a wrapper over another stream to add column and line number tracking. It is used only for asm printing. This patch moves the its creation down to where we know we are printing assembly. This has the following advantages: * Simpler lifetime management: std::unique_ptr * We don't compute column and line number of object files :-) llvm-svn: 234535
* [AArch64][FastISel] Fix integer extend optimization.Juergen Ributzka2015-04-091-5/+6
| | | | | | | | | | | | | | The integer extend optimization tries to fold the extend into the load instruction. This requires us to identify if the extend has already been emitted or not and act accordingly on it. The check that was originally performed for this was not sufficient. Besides checking the ValueMap for a mapped register we also need to check if the virtual register has already an associated machine instruction that defines it. This fixes rdar://problem/20470788. llvm-svn: 234529
* Remove duplicated code and consolidate initializers.Eric Christopher2015-04-092-15/+5
| | | | llvm-svn: 234525
* clang-format bits of code to make a followup patch easy to read.Rafael Espindola2015-04-0911-26/+16
| | | | llvm-svn: 234519
* Use a raw_svector_ostream instead of a raw_string_ostream.Rafael Espindola2015-04-091-6/+8
| | | | | | It saves a bit of copying. llvm-svn: 234507
* Don't repeat name in comment. NFC.Rafael Espindola2015-04-094-24/+22
| | | | llvm-svn: 234506
* This reverts commit r234460 and r234461.Rafael Espindola2015-04-093-8/+6
| | | | | | | | | Revert "Add classof implementations to the raw_ostream classes." Revert "Use the cast machinery to remove dummy uses of formatted_raw_ostream." The underlying issue can be fixed without classof. llvm-svn: 234495
* [ARM] support for Cortex-R4/R4FJaved Absar2015-04-092-1/+19
| | | | | | | | | Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
* [mips] Refactor saved-registers bitmask creation in ↵Toma Tabacu2015-04-091-20/+11
| | | | | | | | | | | | | | | | | | | MipsAsmPrinter::printSavedRegsBitmask. NFC. Summary: Make the code more readable by fusing the for-loops together and explicitly checking for each register class. Also, this version is more straightforward because it doesn't assume that FPU registers always come before CPU registers in the CalleeSavedInfo vector. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8033 llvm-svn: 234475
* [AArch64] Add support for dynamic stack alignmentKristof Beyls2015-04-094-43/+172
| | | | | | Differential Revision: http://reviews.llvm.org/D8876 llvm-svn: 234471
* [AArch64] Remove redundant -march option. Also fix a think-o from r234462.Lang Hames2015-04-091-1/+1
| | | | llvm-svn: 234467
* [AArch64] Teach AArch64TargetLowering::getOptimalMemOpType to consider alignmentLang Hames2015-04-091-1/+11
| | | | | | | | | | | | | restrictions when choosing a type for small-memcpy inlining in SelectionDAGBuilder. This ensures that the loads and stores output for the memcpy won't be further expanded during legalization, which would cause the total number of instructions for the memcpy to exceed (often significantly) the inlining thresholds. <rdar://problem/17829180> llvm-svn: 234462
* Use the cast machinery to remove dummy uses of formatted_raw_ostream.Rafael Espindola2015-04-093-6/+8
| | | | | | | If we know we are producing an object, we don't need to wrap the stream in a formatted_raw_ostream anymore. llvm-svn: 234461
* [ARM] make vminnm/vmaxnm work with ?le, ?ge and no-nans-fp-mathScott Douglass2015-04-081-9/+18
| | | | | | | | | | Because -menable-no-nans causes fcmp conditions to be rewritten without 'o' or 'u' the recognition code in needs to cope. Also extended it to handle 'le' and 'ge. Differential Revision: http://reviews.llvm.org/D8725 llvm-svn: 234421
* [mips] [IAS] Do not generate redundant move when expanding lw/sw with symbol.Toma Tabacu2015-04-081-6/+8
| | | | | | | | | | | | | | | | | | Summary: Even though there is no 2nd register operand in the "lw/sw $8, symbol" case, we still try to find one, and we end up with $0, which makes us generate an unnecessary "addu $8, $8, $0" (a.k.a. "move $8, $8"). We can avoid this by checking if the 2nd register operand is different from $0, before generating the addu. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8055 llvm-svn: 234406
* [mips] [IAS] Add support for the BNEZL and BEQZL pseudo-instructions.Toma Tabacu2015-04-081-0/+4
| | | | | | | | | | | | | | | | | Summary: They are of the form "bnezl/beqzl $rs, offset" and expand to "bnel/beql $rs, $zero, offset". These instructions are used in Linux inline assembly. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8540 llvm-svn: 234401
* [ARM][Debug Info] Restore emitting of .cfi_def_cfa_offset for functions ↵Sergey Dmitrouk2015-04-081-1/+2
| | | | | | | | | | | | | | | | without stack frame Summary: Looks like new code from [[ http://reviews.llvm.org/rL222057 | rL222057 ]] doesn't account for early `return` in `ARMFrameLowering::emitPrologue`, which leads to loosing `.cfi_def_cfa_offset` directive for functions without stack frame. Reviewers: echristo, rengolin, asl, t.p.northover Reviewed By: t.p.northover Subscribers: llvm-commits, rengolin, aemerson Differential Revision: http://reviews.llvm.org/D8606 llvm-svn: 234399
* [mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic.Toma Tabacu2015-04-081-4/+2
| | | | | | | | | | | | | | | | Summary: These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs. For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8300 llvm-svn: 234398
* [bpf] support BPF backend as shared libraryAlexei Starovoitov2015-04-081-1/+1
| | | | | | | | | dependencies were not set correctly for shared library build. static was ok Patch by Brenden Blanco. llvm-svn: 234386
* R600/SI: Add some missing overridesTom Stellard2015-04-082-2/+2
| | | | llvm-svn: 234384
* R600/SI: Initial support for assembler and inline assemblyTom Stellard2015-04-0814-133/+1369
| | | | | | | | | | | | | This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
* R600/SI: Add missing SOPK instructionsTom Stellard2015-04-083-13/+72
| | | | llvm-svn: 234380
* R600/SI: Don't print offset0/offset1 DS operands when they are 0Tom Stellard2015-04-081-4/+8
| | | | llvm-svn: 234379
* AArch64: disallow "fmov sD, #-0.0" during assembly.Tim Northover2015-04-071-3/+4
| | | | | | | | | | | | | We weren't checking the sign of the floating point immediate before translating it to "fmov sD, wzr". Similarly for D-regs. Technically "movi vD.2s, #0x80, lsl #24" would work most of the time, but it's not a blessed alias (and I don't think it should be since people expect writing sD to zero out the high lanes, and there's no dD equivalent). So an error it is. rdar://20455398 llvm-svn: 234372
* [ARM] Mark a bunch of .td Operands with type _MEMORY.Ahmed Bougacha2015-04-073-39/+42
| | | | | | | | | | | This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
* [bpf] fix buildAlexei Starovoitov2015-04-072-6/+3
| | | | | | | | fix the build and remove unused variable warnings in Release mode. Patch by Brenden Blanco. llvm-svn: 234349
* AArch64: Don't lower ISD::SELECT to ISD::SELECT_CCMatthias Braun2015-04-072-44/+60
| | | | | | | | | | | | | | | | Instead of lowering SELECT to SELECT_CC which is further lowered later immediately call the SELECT_CC lowering code. This is preferable because: - Avoids an unnecessary roundtrip through the legalization queues with an intermediate node. - More importantly: Lowered operations get visited last leading to SELECT_CC getting visited with legalized operands and unlegalized ones for preexisting SELECT_CC nodes. This does not hurt the current code (hence no testcase) but is required for another patch I am working on. Differential Revision: http://reviews.llvm.org/D8187 llvm-svn: 234334
* [mips] [IAS] Allow .set assignments for already defined symbols.Toma Tabacu2015-04-071-5/+1
| | | | | | | | | | | | | | | | Summary: This is not possible when using the IAS for MIPS, but it is possible when using the IAS for other architectures and when using GAS for MIPS. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8578 llvm-svn: 234316
* Refactor a lot of duplicated code for stub output.Rafael Espindola2015-04-077-127/+1
| | | | | | | This also moves it earlier so that it they are produced before we print an end symbol for the data section. llvm-svn: 234315
* Silencing several "enumeral and non-enumeral type in conditional expression" ↵Aaron Ballman2015-04-071-4/+4
| | | | | | warnings; NFC. llvm-svn: 234314
* CodeGen: Stop using DIDescriptor::is*() and auto-castingDuncan P. N. Exon Smith2015-04-062-5/+2
| | | | | | Same as r234255, but for lib/CodeGen and lib/Target. llvm-svn: 234258
* ARM: do not relax Thumb1 -> Thumb2 if only Thumb1 is available.Tim Northover2015-04-064-13/+16
| | | | | | | | | | | | | | | After recognising that a certain narrow instruction might need a relocation to be represented, we used to unconditionally relax it to a Thumb2 instruction to permit this. Unfortunately, some CPUs (e.g. v6m) don't even have most Thumb2 instructions, so we end up emitting a completely invalid instruction. Theoretically, ELF does have relocations for these situations; but they are fairly unusable with such short ranges and the ABI document even says they're documented "for completeness". So an error is probably better there too. rdar://20391953 llvm-svn: 234195
* [X86][SSE] Use (V)PINSRB for direct byte insertion in 16i8 buildvector on ↵Simon Pilgrim2015-04-061-0/+23
| | | | | | | | | | | | SSE4.1 targets This patch allows SSE4.1 targets to use (V)PINSRB to create 16i8 vectors by inserting i8 scalars directly into a XMM register instead of merging pairs of i8 scalars into a i16 and using the SSE2 PINSRW instruction. This allows folding of byte loads and reduces scalar register usage as well. Differential Revision: http://reviews.llvm.org/D8839 llvm-svn: 234193
* Remove unnecessary uses of AliasedSymbol.Rafael Espindola2015-04-061-2/+2
| | | | | | | | | As pr19627 points out, every use of AliasedSymbol is likely a bug. The main use was to avoid the oddity of a variable showing up as undefined. That was fixed in r233995, which made these calls nops. llvm-svn: 234169
* Store the sh_link of ARM_EXIDX directly in MCSectionELF.Rafael Espindola2015-04-061-8/+7
| | | | | | This avoids some pretty horrible and broken name based section handling. llvm-svn: 234142
* Implement unique sections with an unique ID.Rafael Espindola2015-04-041-2/+1
| | | | | | | | | | | This allows the compiler/assembly programmer to switch back to a section. This in turn fixes the bootstrap failure on powerpc (tested on gcc110) without changing the ppc codegen at all. I will try to cleanup the various getELFSection overloads in a followup patch. Just using a default argument now would lead to ambiguities. llvm-svn: 234099
* [X86] Apply AddedComplexity consistently for similar patterns. This keeps ↵Craig Topper2015-04-041-4/+8
| | | | | | them together in the DAGISel tables and reduces table size slightly. llvm-svn: 234086
* [X86] Add a comment about the change in r234075.Craig Topper2015-04-041-0/+2
| | | | llvm-svn: 234079
* [X86] Don't use GR64 register 'and with immediate' instructions if the ↵Craig Topper2015-04-041-0/+5
| | | | | | | | | | immediate is zero in the upper 33-bits or upper 57-bits. Use GR32 instructions instead. Previously the patterns didn't have high enough priority and we would only use the GR32 form if the only the upper 32 or 56 bits were zero. Fixes PR23100. llvm-svn: 234075
* [WinEH] Sink UnwindHelp completely out of IRDavid Majnemer2015-04-031-8/+19
| | | | | | | | We don't need to represent UnwindHelp in IR. Instead, we can use the knowledge that we are emitting the parent function to decide if we should create the UnwindHelp stack object. llvm-svn: 234061
* [opaque pointer type] More GEP IRBuilder API migrations...David Blaikie2015-04-032-3/+6
| | | | llvm-svn: 234058
* [opaque pointer type] More GEP API migrations in IRBuilder usesDavid Blaikie2015-04-031-3/+5
| | | | | | | | | | | | | The plan here is to push the API changes out from the common components (like Constant::getGetElementPtr and IRBuilder::CreateGEP related functions) and just update callers to either pass the type if it's obvious, or pass null. Do this with LoadInst as well and anything else that comes up, then to start porting specific uses to not pass null anymore - this may require some refactoring in each case. llvm-svn: 234042
* CodeGen: Assert that inlined-at locations agreeDuncan P. N. Exon Smith2015-04-031-0/+2
| | | | | | | | | | | | | | | | | As a follow-up to r234021, assert that a debug info intrinsic variable's `MDLocalVariable::getInlinedAt()` always matches the `MDLocation::getInlinedAt()` of its `!dbg` attachment. The goal here is to get rid of `MDLocalVariable::getInlinedAt()` entirely (PR22778), but I'll let these assertions bake for a while first. If you have an out-of-tree backend that just broke, you're probably attaching the wrong `DebugLoc` to a `DBG_VALUE` instruction. The one you want is the location that was attached to the corresponding `@llvm.dbg.declare` or `@llvm.dbg.value` call that you started with. llvm-svn: 234038
* [X86] Added SSE4.2 CRC32 memory folding patterns + testsSimon Pilgrim2015-04-031-0/+2
| | | | llvm-svn: 234013
* [PowerPC] Enable splat generation for BUILD_VECTOR with little endianBill Schmidt2015-04-032-37/+2
| | | | | | | | | | | | | | | | | | | When enabling PPC64LE, I disabled some optimizations of BUILD_VECTOR nodes for little endian because wrong results were produced. I've subsequently investigated and found this is due to a call to BuildVectorSDNode::isConstantSplat that was always specifying big-endian. With this changed to correctly identify the target endianness, the optimizations work as expected. I found another case of a call to the same method with big-endian hardcoded, in PPC::isAllNegativeZeroVector(). I discovered this was an orphaned method with no callers, so I've just removed it. The existing test/CodeGen/PowerPC/vec_constants.ll checks these optimizations, so for testing I've just added a variant for little endian. llvm-svn: 234011
* [X86][3DNow] Added 3DNow! memory folding patterns + testsSimon Pilgrim2015-04-031-0/+28
| | | | llvm-svn: 234008
* MC: For variable symbols, maintain MCSymbol::Section as a cache.Peter Collingbourne2015-04-031-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes PR19582. Previously, when an asm assignment (.set or =) was created, we would look up the section immediately in MCSymbol::setVariableValue. This caused symbols to receive the wrong section if the RHS of the assignment had not been seen yet. This had a knock-on effect in the object file emitters, causing them to emit extra symbols, or to give symbols the wrong visibility or the wrong section. For example, in the following asm: .data .Llocal: .text leaq .Llocal1(%rip), %rdi .Llocal1 = .Llocal2 .Llocal2 = .Llocal the first assignment would give .Llocal1 a null section, which would never get fixed up by the second assignment. This would cause the ELF object file emitter to consider .Llocal1 to be an undefined symbol and give it external linkage, even though .Llocal1 should not have been emitted at all in the object file. Or in the following asm: alias_to_local = Ltmp0 Ltmp0: the Mach-O object file emitter would give the alias_to_local symbol a n_type of N_SECT and a n_sect of 0. This is invalid under the Mach-O specification, which requires N_SECT symbols to receive a non-zero section number if the symbol is defined in a section in the object file. https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/MachORuntime/#//apple_ref/c/tag/nlist After this change we do not look up the section when the assignment is created, but instead look it up on demand and store it in Section, which is treated as a cache if the symbol is a variable symbol. This change also fixes a bug in MCExpr::FindAssociatedSection. Previously, if we saw a subtraction, we would return the first referenced section, even in cases where we should have been returning the absolute pseudo-section. Now we always return the absolute pseudo-section for expressions that subtract two section-derived expressions. This isn't always correct (e.g. if one of the sections ends up being laid out at an absolute address), but it's probably the best we can do without more context. This allows us to remove code in two places where we appear to have been working around this bug, in MachObjectWriter::markAbsoluteVariableSymbols and in X86AsmPrinter::EmitStartOfAsmFile. Re-applies r233595 (aka D8586), which was reverted in r233898. Differential Revision: http://reviews.llvm.org/D8798 llvm-svn: 233995
* ARM: Handle physreg targets in RegPair hints gracefullyMatthias Braun2015-04-031-6/+15
| | | | | | | | Register coalescing can change the target of a RegPair hint to a physreg, we should not crash on this. This also slightly improved the way ARMBaseRegisterInfo::updateRegAllocHint() works. llvm-svn: 233987
* [AVX] Improve insertion of i8 or i16 into low element of 256-bit zero vectorSanjay Patel2015-04-021-3/+13
| | | | | | | | | | | | | | | | | Without this patch, we split the 256-bit vector into halves and produced something like: movzwl (%rdi), %eax vmovd %eax, %xmm0 vxorps %xmm1, %xmm1, %xmm1 vblendps $15, %ymm0, %ymm1, %ymm0 ## ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] Now, we eliminate the xor and blend because those zeros are free with the vmovd: movzwl (%rdi), %eax vmovd %eax, %xmm0 This should be the final fix needed to resolve PR22685: https://llvm.org/bugs/show_bug.cgi?id=22685 llvm-svn: 233941
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