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* [Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register setNemanja Ivanovic2016-10-043-6/+81
| | | | | | | | | | | | | This patch corresponds to review: The newly added VSX D-Form (register + offset) memory ops target the upper half of the VSX register set. The existing ones target the lower half. In order to unify these and have the ability to target all the VSX registers using D-Form operations, this patch defines Pseudo-ops for the loads/stores which are expanded post-RA. The expansion then choses the correct opcode based on the register that was allocated for the operation. llvm-svn: 283212
* [mips][fastisel] Consider soft-float an unsupported floating point modeSimon Dardis2016-10-041-2/+6
| | | | | | | | | | | Treat soft-float as unsupported for fast-isel. Additionally, ensure we check that lowering f32 arguments also considers the case of soft-float mode. Reviewers: ehostunreach, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D24505 llvm-svn: 283209
* Consistent fp denormal mode names. NFC.Sjoerd Meijer2016-10-042-5/+5
| | | | | | | | | This fixes the inconsistency of the fp denormal option names: in LLVM this was DenormalType, but in Clang this is DenormalMode which seems better. Differential Revision: https://reviews.llvm.org/D24906 llvm-svn: 283192
* [Power9] Part-word VSX integer scalar loads/stores and sign extend instructionsNemanja Ivanovic2016-10-0418-157/+582
| | | | | | | | | | | | | | | | | | This patch corresponds to review: https://reviews.llvm.org/D23155 This patch removes the VSHRC register class (based on D20310) and adds exploitation of the Power9 sub-word integer loads into VSX registers as well as vector sign extensions. The new instructions are useful for a few purposes: Int to Fp conversions of 1 or 2-byte values loaded from memory Building vectors of 1 or 2-byte integers with values loaded from memory Storing individual 1 or 2-byte elements from integer vectors This patch implements all of those uses. llvm-svn: 283190
* [X86] Add MOV8rm_NOREX to switch in isReallyTriviallyReMaterializable to ↵Craig Topper2016-10-041-0/+1
| | | | | | match MOV8rm. llvm-svn: 283184
* AMDGPU: Refactor indirect vector loweringMatt Arsenault2016-10-041-36/+42
| | | | | | | Allow inserting multiple instructions in the expanded loop. llvm-svn: 283177
* AMDGPU: Factor SGPR spilling into separate functionsMatt Arsenault2016-10-042-129/+166
| | | | llvm-svn: 283175
* [WebAssembly] Update to more stack-machine-oriented terminology.Dan Gohman2016-10-038-28/+36
| | | | | | | | WebAssembly has officially switched from being an AST to being a stack machine. Update various bits of terminology and README.md entries accordingly. llvm-svn: 283154
* [WebAssemby] Clean up an obsolete comment.Dan Gohman2016-10-031-2/+1
| | | | | | The comment is present inside the body of GetVRegDef. llvm-svn: 283153
* TargetMachine: Make the win32-macho workaround more specific.Matthias Braun2016-10-031-1/+1
| | | | | | | | | This is to avoid problems with win32 + ELF which surprisingly happens a lot in practice: If a user just specifies -march on the commandline the object format changes along with the architecture to ELF in many instances while the OS stays with the default/host OS. llvm-svn: 283151
* [WebAssembly] Delete an unused function. NFC.Dan Gohman2016-10-031-5/+0
| | | | llvm-svn: 283150
* [WebAssembly] Fix indentation. NFC.Dan Gohman2016-10-031-1/+4
| | | | llvm-svn: 283147
* [WebAssembly] Rename OPERAND_FP32IMM to OPERAND_F32IMM.Dan Gohman2016-10-034-8/+8
| | | | | | | WebAssembly documentation consistently says "f32" rather than "fp32" to describe 32-bit floating-point. llvm-svn: 283146
* [AArch64][RegisterBankInfo] Add getSameKindofOperandsMapping.Quentin Colombet2016-10-032-26/+54
| | | | | | | | | | Refactor the code so that the same function can be used for all instructions with all the same operands for up to 3 operands. This is going to be useful for cast instructions. NFC. llvm-svn: 283144
* [RDF] Fix liveness propagation through shadowsKrzysztof Parzyszek2016-10-031-29/+7
| | | | | | | | Each shadow only represents data flow that is restricted to its reaching def. Propagating more than that could lead to spurious register liveness, resulting in extra (incorrectly) block live-ins. llvm-svn: 283143
* AArch64Subtarget: Remove unused CPUString fieldMatthias Braun2016-10-032-7/+6
| | | | llvm-svn: 283142
* X86: Do not produce GOT relocations on windowsMatthias Braun2016-10-031-2/+5
| | | | | | | | | | Windows has no GOT relocations the way elf/darwin has. Some people use x86_64-pc-win32-macho to build EFI firmware; Do not produce GOT relocations for this target. Differential Revision: https://reviews.llvm.org/D24627 llvm-svn: 283140
* [AMDGPU] Pass optimization level to SelectionDAGISelKonstantin Zhuravlyov2016-10-033-8/+11
| | | | llvm-svn: 283133
* [AMDGPU] Sign extend AShr when promoting (instead of zero extending)Konstantin Zhuravlyov2016-10-031-2/+2
| | | | llvm-svn: 283130
* [RDF] Further improve readability of the graphKrzysztof Parzyszek2016-10-031-11/+14
| | | | | | Print target basic block for a branch. llvm-svn: 283126
* [RDF] Replace RegisterAliasInfo with target-independent code using lane masksKrzysztof Parzyszek2016-10-0310-430/+369
| | | | llvm-svn: 283122
* [x86, SSE/AVX] allow 128/256-bit lowering for copysign vector intrinsics ↵Sanjay Patel2016-10-031-17/+27
| | | | | | | | | | | | | | | | (PR30433) This should fix: https://llvm.org/bugs/show_bug.cgi?id=30433 There are a couple of open questions about the codegen: 1. Should we let scalar ops be scalars and avoid vector constant loads/splats? 2. Should we have a pass to combine constants such as the inverted pair that we have here? Differential Revision: https://reviews.llvm.org/D25165 llvm-svn: 283119
* AMDGPU: Fix typoMatt Arsenault2016-10-031-1/+1
| | | | llvm-svn: 283108
* Add new target hooks for LoadStoreVectorizerVolkan Keles2016-10-032-2/+2
| | | | | | | | | | | | Summary: Added 6 new target hooks for the vectorizer in order to filter types, handle size constraints and decide how to split chains. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, mzolotukhin, wdng, llvm-commits, nhaehnle Differential Revision: https://reviews.llvm.org/D24727 llvm-svn: 283099
* [ARM] Code size optimisation to lower udiv+urem to udiv+mls instead of aSjoerd Meijer2016-10-031-1/+19
| | | | | | | | | | | | | | | library call to __aeabi_uidivmod. This is an improved implementation of r280808, see also D24133, that got reverted because isel was stuck in a loop. That was caused by the optimisation incorrectly triggering on i64 ints, which shouldn't happen because there is no 64bit hwdiv support; that put isel's type legalization and this optimisation in a loop. A native ARM compiler and testing now shows that this is fixed. Patch mostly by Pablo Barrio. Differential Revision: https://reviews.llvm.org/D25077 llvm-svn: 283098
* [AMDGPU] Remove unused variables from SIOptimizeExecMaskingKonstantin Zhuravlyov2016-10-031-3/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D25110 llvm-svn: 283087
* [PowerPC] Account for the ELFv2 function prologue during branch selectionHal Finkel2016-10-032-2/+18
| | | | | | | | | | | | | | | | The PPC branch-selection pass, which performs branch relaxation, needs to account for the padding that might be introduced to satisfy block alignment requirements. We were assuming that the first block was at offset zero (i.e. had the alignment of the function itself), but under the ELFv2 ABI, a global entry function prologue is added to the first block, and it is a two-instruction sequence (i.e. eight-bytes long). If the function has 16-byte alignment, the fact that the first block is eight bytes offset from the start of the function is relevant to calculating where padding will be added in between later blocks. Unfortunately, I don't have a small test case. llvm-svn: 283086
* [AVX-512] Remove isCheapAsAMove flag from VMOVAPSZ128rm_NOVLX and friends.Craig Topper2016-10-031-1/+1
| | | | | | This was accidentally copy and pasted from other Pseudos in the file. llvm-svn: 283084
* [X86] Mark all sizes of (V)MOVUPD as trivially rematerializable.Craig Topper2016-10-033-24/+23
| | | | | | I don't know for sure that we truly needs this, but its the only vector load that isn't rematerializable. Making it consistent allows it to not be a special case in the td files. llvm-svn: 283083
* [X86][AVX2] Add support for combining target shuffles to VPERMD/VPERMPSSimon Pilgrim2016-10-021-3/+23
| | | | llvm-svn: 283080
* [X86][AVX] Ensure broadcast loads respect dependenciesSimon Pilgrim2016-10-021-0/+11
| | | | | | | | | | | | To allow broadcast loads of a non-zero'th vector element, lowerVectorShuffleAsBroadcast can replace a load with a new load with an adjusted address, but unfortunately we weren't ensuring that the new load respected the same dependencies. This patch adds a TokenFactor and updates all dependencies of the old load to reference the new load instead. Bug found during internal testing. Differential Revision: https://reviews.llvm.org/D25039 llvm-svn: 283070
* [X86] Don't set i64 ADDC/ADDE/SUBC/SUBE as Custom if the target isn't ↵Craig Topper2016-10-021-7/+4
| | | | | | 64-bit. This way we don't have to catch them and do nothing with them in ReplaceNodeResults. llvm-svn: 283066
* [X86] Fix indentation. NFCCraig Topper2016-10-021-1/+1
| | | | llvm-svn: 283065
* [PowerPC] Refactor soft-float support, and enable PPC64 soft floatHal Finkel2016-10-025-26/+43
| | | | | | | | | | | | | | | | | | | | | | | This change enables soft-float for PowerPC64, and also makes soft-float disable all vector instruction sets for both 32-bit and 64-bit modes. This latter part is necessary because the PPC backend canonicalizes many Altivec vector types to floating-point types, and so soft-float breaks scalarization support for many operations. Both for embedded targets and for operating-system kernels desiring soft-float support, it seems reasonable that disabling hardware floating-point also disables vector instructions (embedded targets without hardware floating point support are unlikely to have Altivec, etc. and operating system kernels desiring not to use floating-point registers to lower syscall cost are unlikely to want to use vector registers either). If someone needs this to work, we'll need to change the fact that we promote many Altivec operations to act on v4f32. To make it possible to disable Altivec when soft-float is enabled, hardware floating-point support needs to be expressed as a positive feature, like the others, and not a negative feature, because target features cannot have dependencies on the disabling of some other feature. So +soft-float has now become -hard-float. Fixes PR26970. llvm-svn: 283060
* [X86][SSE] Cleaned up shuffle decode assertion messagesSimon Pilgrim2016-10-011-7/+11
| | | | llvm-svn: 283050
* Fix signed/unsigned warningSimon Pilgrim2016-10-011-2/+2
| | | | llvm-svn: 283041
* [X86][SSE] Add support for combining target shuffles to binary BLENDSimon Pilgrim2016-10-011-4/+30
| | | | | | We already had support for 1-input BLEND with zero - this adds support for 2-input BLEND as well. llvm-svn: 283040
* [X86][SSE] Always combine target shuffles to MOVSD/MOVSSSimon Pilgrim2016-10-013-10/+19
| | | | | | | | Now we can commute to BLENDPD/BLENDPS on SSE41+ targets if necessary, so simplify the combine matching where we can. This required me to add a couple of scalar math movsd/moss fold patterns that hadn't been needed in the past. llvm-svn: 283038
* [X86][SSE] Enable commutation from MOVSD/MOVSS to BLENDPD/BLENDPS on SSE41+ ↵Simon Pilgrim2016-10-012-0/+31
| | | | | | | | | | | | targets Instead of selecting between MOVSD/MOVSS and BLENDPD/BLENDPS at shuffle lowering by subtarget this will help us select the instruction based on actual commutation requirements. We could possibly add BLENDPD/BLENDPS -> MOVSD/MOVSS commutation and MOVSD/MOVSS memory folding using a similar approach if it proves useful I avoided adding AVX512 handling as I'm not sure when we should be making use of VBLENDPD/VBLENDPS on EVEX targets llvm-svn: 283037
* [X86] Cleanup patterns for using VMOVDDUP for broadcasts.Craig Topper2016-10-011-6/+6
| | | | | | | | -Remove OptForSize. Not all of the backend follows the same rules for creating broadcasts and there is no conflicting pattern. -Don't stop selecting VEX VMOVDDUP when AVX512 is supported. We need VLX for EVEX VMOVDDUP. -Only use VMOVDDUP for v2i64 broadcasts if AVX2 is not supported. llvm-svn: 283020
* Revert "Use StringRef instead of raw pointer in TargetRegistry API (NFC)"Mehdi Amini2016-10-011-2/+2
| | | | | | This reverts commit r283017. Creates an infinite loop somehow. llvm-svn: 283019
* Use StringRef instead of raw pointers in MCAsmInfo/MCInstrInfo APIs (NFC)Mehdi Amini2016-10-017-14/+14
| | | | llvm-svn: 283018
* Use StringRef instead of raw pointer in TargetRegistry API (NFC)Mehdi Amini2016-10-011-2/+2
| | | | llvm-svn: 283017
* [AVX-512] Add EVEX versions of VPBROADCASTW patterns with truncated i32 loads.Craig Topper2016-10-012-1/+18
| | | | llvm-svn: 283015
* Use StringRef in Datalayout API (NFC)Mehdi Amini2016-10-012-2/+2
| | | | llvm-svn: 283013
* Revert "Use StringRef in Datalayout API (NFC)"Mehdi Amini2016-10-011-1/+1
| | | | | | This reverts commit r283009. Bots are broken. llvm-svn: 283011
* Use StringRef in Datalayout API (NFC)Mehdi Amini2016-10-011-1/+1
| | | | llvm-svn: 283009
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-01158-270/+174
| | | | llvm-svn: 283004
* Revert "AMDGPU: Don't use offen if it is 0"Mehdi Amini2016-10-012-100/+14
| | | | | | | This reverts commit r282999. Tests are not passing: http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules/builds/20038 llvm-svn: 283003
* Remove TargetTriple from AArch64MCInstLower as it's used in few placesEric Christopher2016-10-011-3/+4
| | | | | | and can be pulled from the TargetMachine. NFC. llvm-svn: 283000
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