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* [PowerPC] Fix switch warnings from r183841.Bill Schmidt2013-06-122-2/+3
| | | | | | | Introducing PRED_BAD caused some unexpected warnings that are now suppressed. llvm-svn: 183854
* [PowerPC] Expose some calling convention functions in PPCISelLowering.h.Bill Schmidt2013-06-122-29/+32
| | | | | | | | | | | | | | This is a preparatory patch for fast-isel support. The instruction selector will need to access some functions in PPCGenCallingConv.inc, which in turn requires several helper functions to be defined. These are currently defined near the only use of PCCGenCallingConv.inc, inside PPCISelLowering.cpp. This patch moves the declaration of the functions into the associated header file to provide the needed visibility. No functional change intended. llvm-svn: 183844
* Add artificial PRED_BAD to PPC::Predicate enumeration.Bill Schmidt2013-06-121-1/+2
| | | | | | | | Allows returning a PPC::Predicate from a function with a no-predicate value possible. Preparatory patch for fast-isel on PPC64 ELF. No behavioral change intended. llvm-svn: 183841
* [MC/DWARF] Support .debug_frame / .debug_line code alignment factorsUlrich Weigand2013-06-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | I've been comparing the object file output of LLVM's integrated assembler against the external assembler on PowerPC, and one area where differences still remain are in DWARF sections. In particular, the GNU assembler generates .debug_frame and .debug_line sections using a code alignment factor of 4, since all PowerPC instructions have size 4 and must be aligned to a multiple of 4. However, current MC code hard-codes a code alignment factor of 1. This patch changes this by adding a "minimum instruction alignment" data element to MCAsmInfo and using this as code alignment factor. This requires passing a MCContext into MCDwarfLineAddr::Encode and MCDwarfLineAddr::EncodeAdvanceLoc. Note that one caller, MCDwarfLineAddr::Write, didn't actually have that information available. However, it turns out that this routine is in fact never used in the whole code base, so the patch simply removes it. If it turns out to be needed again at a later time, it could be re-added with an updated interface. llvm-svn: 183834
* Fix gcc -flto build, by adding LLVM_ATTRIBUTE_USED toPatrik Hagglund2013-06-121-0/+1
| | | | | | LLVMX86CompilationCallback2, called from inline asm. llvm-svn: 183824
* Correct the def registers for the 8bit x86 divide instructions toEric Christopher2013-06-111-4/+4
| | | | | | | match the comments and what the instruction actually does. Noticed on inspection. llvm-svn: 183809
* Use the Copy we defined above here.Eric Christopher2013-06-111-2/+2
| | | | llvm-svn: 183808
* Fix CMakeLists.Akira Hatanaka2013-06-111-0/+1
| | | | llvm-svn: 183804
* [mips] Add an IR transformation pass that optimizes calls to sqrt.Akira Hatanaka2013-06-113-1/+177
| | | | | | | | | The pass emits a call to sqrt that has attribute "read-none". This call will be converted to an ISD::FSQRT node during DAG construction, which will turn into a mips native sqrt instruction. llvm-svn: 183802
* ARM FastISel fix sext/zext foldJF Bastien2013-06-111-19/+36
| | | | | | | | | | | Sign- and zero-extension folding was slightly incorrect because it wasn't checking that the shift on extensions was zero. Further, I recently added AND rd, rn, #255 as a form of 8-bit zero extension, and failed to add the folding code for it. This patch fixes both issues. This patch fixes both, and the test should remain the same: test/CodeGen/ARM/fast-isel-fold.ll llvm-svn: 183794
* [mips] Use function TargetInstrInfo::getRegClass.Akira Hatanaka2013-06-112-6/+9
| | | | | | No functionality changes. llvm-svn: 183767
* R600: Make helper functions static.Benjamin Kramer2013-06-111-4/+5
| | | | llvm-svn: 183744
* Rework r183728, suppress assert(0) for now. Its behavior depends on ↵NAKAMURA Takumi2013-06-111-1/+4
| | | | | | | assertions on win32 hosts. FIXME: Introduce yet another checker but assert(0). llvm-svn: 183736
* It adds support for negative zero offsets for loads and stores.Mihai Popa2013-06-111-1/+1
| | | | | | | Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value. Behavior already present for Thumb2. llvm-svn: 183734
* This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These ↵Mihai Popa2013-06-112-4/+15
| | | | | | are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3. llvm-svn: 183733
* ARM: Enforce decoding rules for VLDn instructionsAmaury de la Vieuville2013-06-112-68/+76
| | | | llvm-svn: 183731
* ARM: Fix STREX/LDREX reecodingAmaury de la Vieuville2013-06-111-10/+28
| | | | | | The decoded MCInst wasn't reencoded as the same instruction llvm-svn: 183729
* Tweak a couple of tests on win32 hosts with +Asserts.NAKAMURA Takumi2013-06-111-1/+1
| | | | | | | | - Don't use assert(0), or tests may pass or fail according to assertions. - For now, The tests are marked as XFAIL for win32 hosts. FIXME: Could we avoid XFAIL to specify triple in the RUN lines? llvm-svn: 183728
* ARMAsmBackend.cpp: Use Triple::isOSBinFormatCOFF() instead of isOSWindows().NAKAMURA Takumi2013-06-111-1/+1
| | | | | | FYI, isOSBinFormatCOFF() is as same as isOSWindows(), on trunk. llvm-svn: 183727
* Whitespace.NAKAMURA Takumi2013-06-111-5/+5
| | | | llvm-svn: 183726
* ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.Tim Northover2013-06-103-1/+23
| | | | | | | | | | | Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some only support Thumb mode (M-class ones currently). This makes sure such CPUs default to the correct mode and makes the AsmParser diagnose an attempt to switch modes incorrectly. rdar://14024354 llvm-svn: 183710
* X86: Stop LEA64_32r doing unspeakable things to its arguments.Tim Northover2013-06-105-70/+221
| | | | | | | | | | | | Previously LEA64_32r went through virtually the entire backend thinking it was using 32-bit registers until its blissful illusions were cruelly snatched away by MCInstLower and 64-bit equivalents were substituted at the last minute. This patch makes it behave normally, and take 64-bit registers as sources all the way through. Previous uses (for 32-bit arithmetic) are accommodated via SUBREG_TO_REG instructions which make the types and classes agree properly. llvm-svn: 183693
* [PowerPC] Support extended sc mnemonicUlrich Weigand2013-06-101-0/+2
| | | | | | | | | A plain "sc" without argument is supposed to be treated like "sc 0" by the assembler. This patch adds a corresponding alias. Problem reported by Joerg Sonnenberger. llvm-svn: 183687
* [PowerPC] Support branch mnemonics with implied CR0Ulrich Weigand2013-06-101-0/+11
| | | | | | | | | | The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
* [PowerPC] Use multiclass to generate extended branch mnemonicsUlrich Weigand2013-06-101-51/+22
| | | | | | | | | This patch removes some redundancy by generating the extended branch mnemonics via a multiclass. No change in behaviour expected. llvm-svn: 183685
* Silencing an MSVC warning about comparing signed and unsigned values.Aaron Ballman2013-06-101-1/+1
| | | | llvm-svn: 183682
* Fix misleading comments in ARMAsmParserAmaury de la Vieuville2013-06-101-6/+6
| | | | llvm-svn: 183657
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-107-2/+157
| | | | | | ISB should only accepts full system sync, other options are reserved llvm-svn: 183656
* [NVPTX] Remove old CONST_NOT_GEN address space that is not being used ↵Justin Holewinski2013-06-103-39/+11
| | | | | | anymore and causes constants to be emitted in the global address space llvm-svn: 183652
* Fix a regression I introduced when I expanded the complex pseudos inReed Kotler2013-06-092-9/+10
| | | | | | | | | the Mips16 port. A few of the psuedos could either take signed or unsigned arguments and I did not distinguish the case and improperly rejected some valid cases that the assembler had previously accepted when they were pure pseudos that expanded as assembly instructions. llvm-svn: 183633
* Fix ARM unwind opcode assembler in several cases.Logan Chien2013-06-093-169/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes to ARM unwind opcode assembler: * Fix multiple .save or .vsave directives. Besides, the order is preserved now. * For the directives which will generate multiple opcodes, such as ".save {r0-r11}", the order of the unwind opcode is fixed now, i.e. the registers with less encoding value are popped first. * Fix the $sp offset calculation. Now, we can use the .setfp, .pad, .save, and .vsave directives at any order. Changes to test cases: * Add test cases to check the order of multiple opcodes for the .save directive. * Fix the incorrect $sp offset in the test case. The stack pointer offset specified in the test case was incorrect. (Changed test cases: ehabi-mc-section.ll and ehabi-mc.ll) * The opcode to restore $sp are slightly reordered. The behavior are not changed, and the new output is same as the output of GNU as. (Changed test cases: eh-directive-pad.s and eh-directive-setfp.s) llvm-svn: 183627
* Removed PackedDouble domain from scalar instructions. Added more formats for ↵Elena Demikhovsky2013-06-092-43/+60
| | | | | | the scalar stuff. llvm-svn: 183626
* ARM FastISel fix load register classesJF Bastien2013-06-091-4/+4
| | | | | | | | The register classes when emitting loads weren't quite restricting enough, leading to MI verification failure on the result register. These are new failures that weren't there the first time I tried enabling ARM FastISel for new targets. llvm-svn: 183624
* [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc ↵Venkatraman Govindaraju2013-06-087-162/+61
| | | | | | backend. llvm-svn: 183613
* ARM: fix VMOVvnf32 decoding when ambiguous with VCVTAmaury de la Vieuville2013-06-081-0/+4
| | | | | | Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF llvm-svn: 183612
* ARM: enforce SRS decoding constraintsAmaury de la Vieuville2013-06-081-1/+7
| | | | llvm-svn: 183611
* ARM: fix CPS decoding when ambiguous with QADDAmaury de la Vieuville2013-06-082-0/+34
| | | | | | | | | Handle the case when the disassembler table can't tell the difference between some encodings of QADD and CPS. Add some necessary safe guards in CPS decoding as well. llvm-svn: 183610
* ARM: fix VCVT decodingAmaury de la Vieuville2013-06-081-2/+2
| | | | | | UNPRED was reported instead of UNDEF llvm-svn: 183608
* Fix unused variable warning from my previous patch.JF Bastien2013-06-081-0/+1
| | | | llvm-svn: 183601
* [mips] Use a helper function which compares the size of the source andAkira Hatanaka2013-06-082-8/+21
| | | | | | | | destination operands of an instruction. No functionality changes. llvm-svn: 183596
* R600: Use a refined heuristic to choose when switching clauseVincent Lejeune2013-06-072-10/+47
| | | | | | | | | | | | | | | This is using a hint from AMD APP OpenCL Programming Guide with empirically tweaked parameters. I used Unigine Heaven 3.0 to determine best parameters on my system (i7 2600/Radeon 6950/Kernel 3.9.4) the benchmark : it went from 38.8 average fps to 39.6, which is ~3% gain. (Lightmark 2008.2 gain is much more marginal: from 537 to 539) There is no lit test provided as the parameter were determined empirically and it it would be nearly impossiblet to find a test program that check for optimal behavior. llvm-svn: 183593
* R600: Anti dep better handled in tex clauseVincent Lejeune2013-06-071-6/+4
| | | | llvm-svn: 183592
* Remember the anyext patterns.Jakob Stoklund Olesen2013-06-071-0/+2
| | | | llvm-svn: 183589
* Add missing zextloadi1 to i64 patterns. PR16721.Jakob Stoklund Olesen2013-06-071-0/+3
| | | | llvm-svn: 183587
* Disallow i64 div/rem in PPC32 counter loopsHal Finkel2013-06-071-0/+7
| | | | | | | | On PPC32, [su]div,rem on i64 types are transformed into runtime library function calls. As a result, they are not allowed in counter-based loops (the counter-loops verification pass caught this error; this change fixes PR16169). llvm-svn: 183581
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-073-6/+6
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183572
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-077-16/+33
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183571
* Remove unused c'tor.Bill Wendling2013-06-071-7/+2
| | | | llvm-svn: 183570
* R600: Fix calculation of stack offset in AMDGPUFrameLoweringTom Stellard2013-06-071-21/+2
| | | | | | | | | We weren't computing structure size correctly and we were relying on the original alloca instruction to compute the offset, which isn't always reliable. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183568
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-074-8/+10
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183567
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