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* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-16114-0/+28329
| | | | llvm-svn: 160270
* Fix a bug in the 3-address conversion of LEA when one of the operands is anNadav Rotem2012-07-161-0/+7
| | | | | | | | | | | | undef virtual register. The problem is that ProcessImplicitDefs removes the definition of the register and marks all uses as undef. If we lose the undef marker then we get a register which has no def, is not marked as undef. The live interval analysis does not collect information for these virtual registers and we crash in later passes. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 160260
* This CL changes the function prologue and epilogue emitted on X86 when stack ↵Alexey Samsonov2012-07-161-53/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | needs realignment. It is intended to fix PR11468. Old prologue and epilogue looked like this: push %rbp mov %rsp, %rbp and $alignment, %rsp push %r14 push %r15 ... pop %r15 pop %r14 mov %rbp, %rsp pop %rbp The problem was to reference the locations of callee-saved registers in exception handling: locations of callee-saved had to be re-calculated regarding the stack alignment operation. It would take some effort to implement this in LLVM, as currently MachineLocation can only have the form "Register + Offset". Funciton prologue and epilogue are now changed to: push %rbp mov %rsp, %rbp push %14 push %15 and $alignment, %rsp ... lea -$size_of_saved_registers(%rbp), %rsp pop %r15 pop %r14 pop %rbp Reviewed by Chad Rosier. llvm-svn: 160248
* Teach getTargetVShiftNode about TargetConstant nodes.Nadav Rotem2012-07-151-1/+4
| | | | llvm-svn: 160234
* Rename VBROADCASTSDrm into VBROADCASTSDYrm to match the naming convention.Nadav Rotem2012-07-152-3/+8
| | | | | | | | | | Allow the folding of vbroadcastRR to vbroadcastRM, where the memory operand is a spill slot. PR12782. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 160230
* AVX: Fix a bug in getTargetVShiftNode. The shift amount has to be a 128bit ↵Nadav Rotem2012-07-141-1/+7
| | | | | | | | vector with the same element type as the input vector. This is needed because of the patterns we have for the VP[SLL/SRA/SRL][W/D/Q] instructions. llvm-svn: 160222
* This is one of the first steps at moving to replace target-dependent Joel Jones2012-07-131-1/+1
| | | | | | | | | | | | | | | | | | | | intrinsics with target-indepdent intrinsics. The first instruction(s) to be handled are the vector versions of count leading zeros (ctlz). The changes here are to clang so that it generates a target independent vector ctlz when it sees an ARM dependent vector ctlz. The changes in llvm are to match the target independent vector ctlz and in VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM dependent vector ctlzs with target-independent ctlzs. There are also changes to an existing test case in llvm for ARM vector count instructions and a new test for the bitcode upgrade. <rdar://problem/11831778> There is deliberately no test for the change to clang, as so far as I know, no consensus has been reached regarding how to test neon instructions in clang; q.v. <rdar://problem/8762292> llvm-svn: 160200
* Remove variable_ops from call instructions in most targets.Jakob Stoklund Olesen2012-07-1311-46/+44
| | | | | | | | Call instructions are no longer required to be variadic, and variable_ops should only be used for instructions that encode a variable number of arguments, like the ARM stm/ldm instructions. llvm-svn: 160189
* Remove variable_ops from ARM call instructions.Jakob Stoklund Olesen2012-07-133-22/+19
| | | | | | | | | | | | Function argument registers are added to the call SDNode, but InstrEmitter now knows how to make those operands implicit, and the call instruction doesn't have to be variadic. Explicit register operands should only be those that are encoded in the instruction, implicit register operands are for extra dependencies like call argument and return values. llvm-svn: 160188
* The Mips specific relocation R_MIPS_GOT_DISP Jack Carter2012-07-134-4/+12
| | | | | | | | | | is used in cases where global symbols are directly represented in the GOT and we use an offset into the global offset table. This patch adds direct object support for R_MIPS_GOT_DISP. llvm-svn: 160183
* Make helper functions static.Benjamin Kramer2012-07-131-1/+1
| | | | llvm-svn: 160173
* Mark VINSERTI128rm as MayLoad=1. Fixes PR13348.Craig Topper2012-07-131-2/+2
| | | | llvm-svn: 160162
* Give the rdrand instructions a SideEffect flag and a chain so MachineCSE and ↵Benjamin Kramer2012-07-122-4/+5
| | | | | | | | MachineLICM don't touch it. I already had the necessary things in place for IR-level passes but missed the machine passes. llvm-svn: 160137
* Add intrinsics for Ivy Bridge's rdrand instruction.Benjamin Kramer2012-07-123-3/+49
| | | | | | | | | The rdrand/cmov sequence is the same that is emitted by both GCC and ICC. Fixes PR13284. llvm-svn: 160117
* Update GATHER instructions to support 2 read-write operands. Patch from ↵Craig Topper2012-07-124-16/+44
| | | | | | myself and Manman Ren. llvm-svn: 160110
* ARM: fix typo in commentsManman Ren2012-07-111-1/+1
| | | | llvm-svn: 160093
* ARM: Fix optimizeCompare to correctly check safe condition.Manman Ren2012-07-111-9/+14
| | | | | | | | It is safe if CPSR is killed or re-defined. When we are done with the basic block, check whether CPSR is live-out. Do not optimize away cmp if CPSR is live-out. llvm-svn: 160090
* Patch for Mips direct object generation.Jack Carter2012-07-111-0/+8
| | | | | | | | | | | | | | | | | When WriteFragmentData() case FT_align called Asm.getBackend().writeNopData() is called, nothing is done since Mips implementation of writeNopData just returned "true". For some reason this has not caused problems in 32 bit mode, but in 64 bit mode it caused an assert when processing multiple function units. The test case included will assert without this patch. It runs twice with different flags to prevent false positives due to changes in code generation over time. llvm-svn: 160084
* This change removes an "initialization" warning.Jack Carter2012-07-111-4/+3
| | | | | | | | Even though variable in question could not be initialized before use, the code was such that the compiler had no way of knowing that. llvm-svn: 160081
* In register classes in MipsRegisterInfo.td, list the registers in ascendingAkira Hatanaka2012-07-111-99/+114
| | | | | | | | order of binary encoding. Patch by Vladimir Medic. llvm-svn: 160073
* [x86 fast-isel] Per discussion with Eric, add all cases to switch with verboseChad Rosier2012-07-111-1/+8
| | | | | | comments. llvm-svn: 160069
* X86: Update to peephole optimization to move Movr0 before (Sub, Cmp) pair.Manman Ren2012-07-111-1/+22
| | | | | | | When Movr0 is between sub and cmp, we move Movr0 before sub if it enables removal of Cmp. llvm-svn: 160066
* Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.Akira Hatanaka2012-07-112-3/+17
| | | | llvm-svn: 160064
* [x86 fast-isel] Rather then call llvm_unreachable() have fast-isel fall backChad Rosier2012-07-111-1/+1
| | | | | | to Selection DAG isel. Patch by Andrew Kaylor <andrew.kaylor@intel.com>. llvm-svn: 160055
* When ext-loading and trunc-storing vectors to memory, on x86 32bit systems, ↵Nadav Rotem2012-07-111-2/+12
| | | | | | allow loads/stores of 64bit values from xmm registers. llvm-svn: 160044
* Lower RETURNADDR node in Mips backend.Akira Hatanaka2012-07-113-5/+31
| | | | | | Patch by Sasa Stankovic. llvm-svn: 160031
* Mips specific inline asm operand modifier 'L'.Jack Carter2012-07-101-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Low order register of a double word register operand. Operands are defined by the name of the variable they are marked with in the inline assembler code. This is a way to specify that the operand just refers to the low order register for that variable. It is the opposite of modifier 'D' which specifies the high order register. Example: main() { long long ll_input = 0x1111222233334444LL; long long ll_val = 3; int i_result = 0; __asm__ __volatile__( "or %0, %L1, %2" : "=r" (i_result) : "r" (ll_input), "r" (ll_val)); } Which results in: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -8 addu $2, $2, $25 sw $2, 0($sp) lui $2, 13107 ori $3, $2, 17476 <-- Low 32 bits of ll_input lui $2, 4369 ori $4, $2, 8738 <-- High 32 bits of ll_input addiu $5, $zero, 3 <-- Low 32 bits of ll_val addiu $2, $zero, 0 <-- High 32 bits of ll_val #APP or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val #NO_APP addiu $sp, $sp, 8 jr $ra If not direction is done for the long long for 32 bit variables results in using the low 32 bits as ll_val shows. There is an existing bug if 'L' or 'D' is used for the destination register for 32 bit long longs in that the target value will be updated incorrectly for the non-specified part unless explicitly set within the inline asm code. llvm-svn: 160028
* Move [get|set]BasePtrStackAdjustment() from MachineFrameInfo toChad Rosier2012-07-102-4/+19
| | | | | | | X86MachineFunctionInfo as this is currently only used by X86. If this ever becomes an issue on another arch (e.g., ARM) then we can hoist it back out. llvm-svn: 160009
* Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier2012-07-103-14/+106
| | | | | | | | | | | | | X86. Basically, this is a reapplication of r158087 with a few fixes. Specifically, (1) the stack pointer is restored from the base pointer before popping callee-saved registers and (2) in obscure cases (see comments in patch) we must cache the value of the original stack adjustment in the prologue and apply it in the epilogue. rdar://11496434 llvm-svn: 160002
* Improve the loading of load-anyext vectors by allowing the codegen to loadNadav Rotem2012-07-101-27/+54
| | | | | | | | | multiple scalars and insert them into a vector. Next, we shuffle the elements into the correct places, as before. Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the migration of bitcasts happened too late in the SelectionDAG process. llvm-svn: 159991
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-102-8/+8
| | | | | | single-precision resiters) (and do it properly this time! llvm-svn: 159989
* Reverse assembler/disassembler operand order for gather instructions.Craig Topper2012-07-101-36/+11
| | | | llvm-svn: 159983
* ARM: Allow more flexible patterns in NEON formats.Jim Grosbach2012-07-101-53/+53
| | | | | | | | | Some NEON instructions want to match against normal SDNodes for some operand types and Intrinsics for others. For example, CTLZ. To enable this, switch from explicitly requiring Intrinsic on the class templates to using SDPatternOperator instead. llvm-svn: 159974
* Make register Mips::RA allocatable if not in mips16 mode.Akira Hatanaka2012-07-109-37/+88
| | | | llvm-svn: 159971
* Revert r159938 (and r159945) to appease the buildbots.Chad Rosier2012-07-092-8/+8
| | | | llvm-svn: 159960
* X86: implement functions to analyze & synthesize CMOV|SET|JccManman Ren2012-07-091-138/+185
| | | | | | | | | | | getCondFromSETOpc, getCondFromCMovOpc, getSETFromCond, getCMovFromCond No functional change intended. If we want to update the condition code of CMOV|SET|Jcc, we first analyze the opcode to get the condition code, then update the condition code, finally synthesize the new opcode form the new condition code. llvm-svn: 159955
* Reapply r158846.Akira Hatanaka2012-07-091-114/+77
| | | | | | | Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
* Some formatting to keep Clang happyRichard Barton2012-07-091-4/+4
| | | | llvm-svn: 159948
* Oops - correct broken disassembly for VMOVRichard Barton2012-07-091-1/+1
| | | | llvm-svn: 159945
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-092-8/+8
| | | | | | single-precision resiters) llvm-svn: 159938
* Prevent ARM assembler from losing a right shift by #32 applied to a registerRichard Barton2012-07-091-1/+3
| | | | llvm-svn: 159937
* Spelling!Richard Barton2012-07-091-2/+2
| | | | llvm-svn: 159936
* Teach the assembler to use the narrow thumb encodings of various ↵Richard Barton2012-07-091-0/+80
| | | | | | three-register dp instructions where permissable. llvm-svn: 159935
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-079-39/+76
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
* X86: Fix optimizeCompare to correctly check safe condition.Manman Ren2012-07-071-5/+25
| | | | | | | | It is safe if EFLAGS is killed or re-defined. When we are done with the basic block, check whether EFLAGS is live-out. Do not optimize away cmp if EFLAGS is live-out. llvm-svn: 159888
* Fix the naming of ensureAlignment. Per the coding standard function namesChad Rosier2012-07-061-3/+3
| | | | | | should be camel case, and start with a lower case letter. llvm-svn: 159877
* ARM: Add test cleanup entry to the README.Jim Grosbach2012-07-061-0/+21
| | | | llvm-svn: 159864
* revert r159851.Akira Hatanaka2012-07-062-131/+166
| | | | llvm-svn: 159854
* Reapply r158846.Akira Hatanaka2012-07-062-166/+131
| | | | | | Include file MipsGenRegisterInfo.inc. llvm-svn: 159851
* X86: peephole optimization to remove cmp instructionManman Ren2012-07-063-0/+302
| | | | | | | | For each Cmp, we check whether there is an earlier Sub which make Cmp redundant. We handle the case where SUB operates on the same source operands as Cmp, including the case where the two source operands are swapped. llvm-svn: 159838
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