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* Revert "[mips] MIPSR6 Compact branch aliases"Simon Dardis2016-04-122-7/+1
| | | | | | | | This reverts commit r266055. ps4-buildslave2 is highlighting a failure. llvm-svn: 266061
* [SystemZ] Use LDE32 instead of LE, when Offset is small.Jonas Paulsson2016-04-121-1/+7
| | | | | | | | | | | | On z13, if eliminateFrameIndex() chooses LE (and not LEY), immediately transform that LE to LDE32 to avoid partial register dependencies. LEY should be generally preferred for big offsets over an expansion into LAY + LDE32. Reviewed by Ulrich Weigand. llvm-svn: 266060
* [mips] MIPSR6 Compact branch aliasesSimon Dardis2016-04-122-1/+7
| | | | | | | | | | | | Summary: Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D18856 llvm-svn: 266055
* [PPC64] Mark CR0 Live if PPCInstrInfo::optimizeCompareInstr Creates a Use of CR0Chuang-Yu Cheng2016-04-121-0/+4
| | | | | | | | | | | | | | Resolve Bug 27046 (https://llvm.org/bugs/show_bug.cgi?id=27046). The PPCInstrInfo::optimizeCompareInstr function could create a new use of CR0, even if CR0 were previously dead. This patch marks CR0 live if a use of CR0 is created. Author: Tom Jablin (tjablin) Reviewers: hfinkel kbarton cycheng http://reviews.llvm.org/D18884 llvm-svn: 266040
* [PPC64] Use mfocrf in prologue when we only need to save 1 nonvolatile CR fieldChuang-Yu Cheng2016-04-121-8/+16
| | | | | | | | | | | | | | In the ELFv2 ABI, we are not required to save all CR fields. If only one nonvolatile CR field is clobbered, use mfocrf instead of mfcr to selectively save the field, because mfocrf has short latency compares to mfcr. Thanks Nemanja's invaluable hint! Reviewers: nemanjai tjablin hfinkel kbarton http://reviews.llvm.org/D17749 llvm-svn: 266038
* AArch64: Drive-by cleanupMatthias Braun2016-04-121-3/+2
| | | | llvm-svn: 266035
* ARM: use r7 as the frame-pointer on all MachO targets.Tim Northover2016-04-112-13/+10
| | | | | | | | | | | | This is better for a few reasons: + It matches the other tooling for iOS. + It matches EABI in more cases (i.e. Thumb-mode, and in practice we don't use ARM mode). + It leads to infinitesimally smaller code (0.2%, yay!). rdar://25369506 llvm-svn: 266003
* Add __atomic_* lowering to AtomicExpandPass.James Y Knight2016-04-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AtomicExpandPass can now lower atomic load, atomic store, atomicrmw, and cmpxchg instructions to __atomic_* library calls, when the target doesn't support atomics of a given size. This is the first step towards moving all atomic lowering from clang into llvm. When all is done, the behavior of __sync_* builtins, __atomic_* builtins, and C11 atomics will be unified. Previously LLVM would pass everything through to the ISelLowering code. There, unsupported atomic instructions would turn into __sync_* library calls. Because of that behavior, Clang currently avoids emitting llvm IR atomic instructions when this would happen, and emits __atomic_* library functions itself, in the frontend. This change makes LLVM able to emit __atomic_* libcalls, and thus will eventually allow clang to depend on LLVM to do the right thing. It is advantageous to do the new lowering to atomic libcalls in AtomicExpandPass, before ISel time, because it's important that all atomic operations for a given size either lower to __atomic_* libcalls (which may use locks), or native instructions which won't. No mixing and matching. At the moment, this code is enabled only for SPARC, as a demonstration. The next commit will expand support to all of the other targets. Differential Revision: http://reviews.llvm.org/D18200 llvm-svn: 266002
* Swift Calling Convention: swifterror target support.Manman Ren2016-04-1114-7/+219
| | | | | | Differential Revision: http://reviews.llvm.org/D18716 llvm-svn: 265997
* Revert "AMDGPU/SI: Do not generate s_waitcnt after ds_permute/ds_bpermute"Tom Stellard2016-04-111-1/+1
| | | | | | | | This reverts commit r263720. Just confirmed that s_waitcnt is required after ds_permute/ds_bpermute. llvm-svn: 265992
* Fix broken assert, PR24624Hans Wennborg2016-04-111-1/+1
| | | | llvm-svn: 265989
* Test commit.Sriraman Tallam2016-04-111-1/+1
| | | | llvm-svn: 265976
* [mips] Make Static a default relocation model for MIPS codegenPetar Jovanovic2016-04-111-3/+1
| | | | | | | | | | | | This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
* [mips] Trivial corrections to range checked immediates.Daniel Sanders2016-04-113-9/+8
| | | | | | | | | | | | | | Summary: SYNC has a 5-bit unsigned immediate. Move MIPS16-specific pcrel16 operand to Mips16 files. Reviewers: vkalintiris Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18755 llvm-svn: 265947
* [SystemZ] README: remove an implemented idea, add some new onesUlrich Weigand2016-04-111-5/+13
| | | | | | | | | | The note about conditional returns can now be removed, as they are implemented. Let's also add 2 new ones in exchange. Author: koriakin Differential Revision: http://reviews.llvm.org/D18962 llvm-svn: 265944
* [SystemZ] Add SVC instructionUlrich Weigand2016-04-112-0/+15
| | | | | | | | | This is going to be useful for inline assembly only. Author: koriakin Differential Revision: http://reviews.llvm.org/D18952 llvm-svn: 265943
* [ARM] Avoid switching ARM/Thumb mode on .arch/.cpu directiveOliver Stannard2016-04-111-0/+30
| | | | | | | | | | | | | | | | | | | | When we see a .arch or .cpu directive, we should try to avoid switching ARM/Thumb mode if possible. If we do have to switch modes, we also need to emit the correct mapping symbol for the new ISA. We did not do this previously, so could emit ARM code with Thumb mapping symbols (or vice-versa). The GAS behaviour is to always stay in the same mode, and to emit an error on any instructions seen when the current mode is not available on the current target. We can't represent that situation easily (we assume that Thumb mode is available if ModeThumb is set), so we differ from the GAS behaviour when switching to a target that can't support the old mode. I've added a warning for when this implicit mode-switch occurs. Differential Revision: http://reviews.llvm.org/D18955 llvm-svn: 265936
* [SystemZ] Support conditional indirect sibling calls via BCRUlrich Weigand2016-04-115-5/+146
| | | | | | | | | | | | | | | This adds a conditional variant of CallBR instruction, CallBCR. Also, it can be fused with integer comparisons, resulting in one of the new C*BCall instructions. In addition to CallBRCL limitations, this has another one: it won't trigger if the function to call isn't already in %r1 - see f22 in the test for an example (it's also why the loads in tests are volatile). Author: koriakin Differential Revision: http://reviews.llvm.org/D18928 llvm-svn: 265933
* [SystemZ] Remove incorrect CC use for C*BReturn instructionsUlrich Weigand2016-04-111-1/+1
| | | | | | | | | These are fused compare-and-branches, so they obviously don't use CC. Author: koriakin Differential Revision: http://reviews.llvm.org/D18927 llvm-svn: 265932
* [X86] Restrict max long nop length for Lakemont.Andrey Turetskiy2016-04-111-1/+2
| | | | | | | | | Restrict the max length of long nops for Lakemont to 7. Experiments on MCU benchmarks (Dhrystone, Coremark) show that this is the most optimal length. Differential Revision: http://reviews.llvm.org/D18897 llvm-svn: 265924
* [X86][AVX512BW] Add support for v64i8 multipliesSimon Pilgrim2016-04-101-3/+38
| | | | | | | | | | Extend the existing lowering of vXi8 multiplies to support v64i8 on avx512bw targets. I added the Lower512IntArith helper function to help with this - not sure how often this could be used in the future, but it seemed better than putting all that logic inside LowerMUL. Differential Revision: http://reviews.llvm.org/D18937 llvm-svn: 265902
* [X86] Use for loops over types to reduce code for setting up operation actions.Craig Topper2016-04-101-150/+97
| | | | llvm-svn: 265893
* [X86] Remove unnecessary setOperationAction for SRA v2i64/v4i64 when VLX is ↵Craig Topper2016-04-101-2/+0
| | | | | | suppored. This is already done for SSE2/AVX2 which VLX implies. NFC llvm-svn: 265892
* [MC] support TLSDESC and TLSCALL / GNU2 tls dialectDavide Italiano2016-04-091-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D18885 llvm-svn: 265881
* [x86] use BMI 'andn' for logic + compare ops Sanjay Patel2016-04-091-3/+13
| | | | | | | | | | With BMI, we can use 'andn' to save an instruction when the result is only used in a compare. This is related to one of the potential sequences to check 'isfinite' in: https://llvm.org/bugs/show_bug.cgi?id=27164 Differential Revision: http://reviews.llvm.org/D18910 llvm-svn: 265875
* [X86][XOP] Support for VPPERM 2-input shuffle mask decodingSimon Pilgrim2016-04-093-27/+127
| | | | | | | | | | This patch adds support for decoding XOP VPPERM instruction when it represents a basic shuffle. The mask decoding required the existing MCInstrLowering code to be updated to support binary shuffles - the implementation now matches what is done in X86InstrComments.cpp. Differential Revision: http://reviews.llvm.org/D18441 llvm-svn: 265874
* [X86] Use for loops over types to reduce code for setting up operation ↵Craig Topper2016-04-091-149/+78
| | | | | | actions. NFC llvm-svn: 265871
* [X86] Remove calls to setOperationAction that set CTLZ_ZERO_UNDEF for some ↵Craig Topper2016-04-091-16/+0
| | | | | | vector types to Expand. Expand is already set for all operations for all vector types earlier so this is redundant. NFC llvm-svn: 265870
* [SSP] Remove llvm.stackprotectorcheck.Tim Shen2016-04-084-6/+23
| | | | | | | | | | This is a cleanup patch for SSP support in LLVM. There is no functional change. llvm.stackprotectorcheck is not needed, because SelectionDAG isn't actually lowering it in SelectBasicBlock; rather, it adds check code in FinishBasicBlock, ignoring the position where the intrinsic is inserted (See FindSplitPointForStackProtector()). llvm-svn: 265851
* Rangeify a loop. NFC.Hans Wennborg2016-04-081-4/+3
| | | | llvm-svn: 265846
* Remove some redundant variables from X86TargetLowering::LowerDYNAMIC_STACKALLOCHans Wennborg2016-04-081-3/+0
| | | | | | These are already defined, with the same values, a few lines up. NFC. llvm-svn: 265845
* [X86] Fix PR23155 by turning on X86FixupBWInsts by default.Kevin B. Smith2016-04-081-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D18866 llvm-svn: 265830
* [SystemZ] Support conditional sibling calls via BRCLUlrich Weigand2016-04-083-1/+26
| | | | | | | | | | | | This adds a conditional variant of CallJG instruction, CallBRCL. It can be used for conditional sibling calls. Unfortunately, due to IfCvt limitations, it only really works well for functions without arguments. Author: koriakin Differential Revision: http://reviews.llvm.org/D18864 llvm-svn: 265814
* [ARM] Enable SMLAW[B|T] and SMLUW[B|T] instruction selectionSam Parker2016-04-081-0/+138
| | | | | | | | | | Added ISelDAGToDAG functions to enable selection of the smlawb, smlawt, smulwb and smulwt instructions for the ARM backend. Also updated the smul CodeGen test and removed the smulw one. Differential Revision: http://reviews.llvm.org/D18892 llvm-svn: 265793
* [X86] Tidied up shuffle decode function doxygen descriptionsSimon Pilgrim2016-04-082-30/+41
| | | | | | As discussed on D18441 - auto brief is used so we don't need /brief, we don't need to include the function name and added some missing descriptions. llvm-svn: 265785
* CXX_FAST_TLS calling convention: performance improvement for PPC64Chuang-Yu Cheng2016-04-087-1/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the same change on PPC64 as r255821 on AArch64. I have even borrowed his commit message. The access function has a short entry and a short exit, the initialization block is only run the first time. To improve the performance, we want to have a short frame at the entry and exit. We explicitly handle most of the CSRs via copies. Only the CSRs that are not handled via copies will be in CSR_SaveList. Frame lowering and prologue/epilogue insertion will generate a short frame in the entry and exit according to CSR_SaveList. The majority of the CSRs will be handled by register allcoator. Register allocator will try to spill and reload them in the initialization block. We add CSRsViaCopy, it will be explicitly handled during lowering. 1> we first set FunctionLoweringInfo->SplitCSR if conditions are met (the target supports it for the given machine function and the function has only return exits). We also call TLI->initializeSplitCSR to perform initialization. 2> we call TLI->insertCopiesSplitCSR to insert copies from CSRsViaCopy to virtual registers at beginning of the entry block and copies from virtual registers to CSRsViaCopy at beginning of the exit blocks. 3> we also need to make sure the explicit copies will not be eliminated. Author: Tom Jablin (tjablin) Reviewers: hfinkel kbarton cycheng http://reviews.llvm.org/D17533 llvm-svn: 265781
* [mips] Use range-based for loops. NFC.Vasileios Kalintiris2016-04-081-10/+16
| | | | llvm-svn: 265780
* [mips][microMIPS] Add CodeGen support for ADD, ADDIU*, ADDU* and DADD* ↵Zlatko Buljan2016-04-085-67/+188
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16454 llvm-svn: 265772
* [AArch64] Fix a typo in the register class to register bank mapping.Quentin Colombet2016-04-071-1/+1
| | | | | | For GPR family we want the GPR register bank, not FPR! llvm-svn: 265743
* [AArch64] Get rid of some GlobalISel ifdefs.Quentin Colombet2016-04-071-3/+1
| | | | llvm-svn: 265725
* [AArch64] gcc does not like litteral without quotes even on preprocessor macros.Quentin Colombet2016-04-071-1/+1
| | | | llvm-svn: 265720
* [AArch64][CallLowering] Do not build the API if GlobalISel is not built.Quentin Colombet2016-04-072-14/+5
| | | | | | | This gets rid of some ifdefs and dummy implementations that were here just to fill the blanks. llvm-svn: 265719
* [GlobalISel] Add RegBankSelect hooks into the pass pipeline.Quentin Colombet2016-04-071-0/+6
| | | | | | | Now, RegBankSelect will happen after the IRTranslation and the target may optionally add additional passes in between. llvm-svn: 265716
* AMDGPU/SI: Implement atomic load/store for i32 and i64Jan Vesely2016-04-075-24/+111
| | | | | | | | | | Standard load/store instructions with GLC bit set. Reviewers: tstellardAMD, arsenm Differential Revision: http://reviews.llvm.org/D18760 llvm-svn: 265709
* AMDGPU/SI: Add latency for export instructionsTom Stellard2016-04-071-0/+1
| | | | | | | | | | Reviewers: arsenm, nhaehnle Subscribers: nhaehnle, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18599 llvm-svn: 265708
* [RegisterBank] Rename RegisterBank::contains into RegisterBank::covers.Quentin Colombet2016-04-071-4/+4
| | | | llvm-svn: 265695
* [SystemZ] Fix build break from r265689Ulrich Weigand2016-04-071-2/+1
| | | | | | | Fix build error seen on some build bots due to: error: default label in switch which covers all enumeration values llvm-svn: 265693
* [X86]: Fix for PR27251.Kevin B. Smith2016-04-071-3/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D18850 llvm-svn: 265690
* [SystemZ] Implement conditional returnsUlrich Weigand2016-04-076-84/+281
| | | | | | | | | | | | | | | | | | Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
* [PPC] Enable transformations in PPCPassConfig::addIRPasses at O2Ehsan Amiri2016-04-071-1/+1
| | | | | | | | | | | | | | http://reviews.llvm.org/D18562 A large number of testcases has been modified so they pass after this test. One testcase is deleted, because I realized even after undoing the original change that was committed with this testcase, the testcase still passes. So I removed it. The change to one other testcase (test/CodeGen/PowerPC/pr25802.ll) is an arbitrary change to keep it passing. Given the original intention of the testcase, and the fact that fixing it will require some time to change the testcase, we concluded that this quick change will be enough. llvm-svn: 265683
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