Commit message (Collapse) | Author | Age | Files | Lines | ||
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* | In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead of | Ken Dyck | 2009-12-17 | 1 | -1/+1 | |
| | | | | | | | incrementing the simple value type of the 16-bit type, which would give the wrong type if an intemediate MVT (such as i24) were introduced. llvm-svn: 91602 | |||||
* | Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings. | Johnny Chen | 2009-12-16 | 1 | -1/+1 | |
| | | | | llvm-svn: 91571 | |||||
* | Silence a clang warning about the deprecated (but perfectly reasonable in | John McCall | 2009-12-16 | 1 | -2/+2 | |
| | | | | | | context) increment-of-bool idiom. llvm-svn: 91564 | |||||
* | Mark STREX* as earlyclobber for the success result register. | Jim Grosbach | 2009-12-16 | 2 | -2/+2 | |
| | | | | llvm-svn: 91555 | |||||
* | Add encoding bits for some Thumb instructions. Plus explicitly set the top two | Johnny Chen | 2009-12-16 | 3 | -10/+18 | |
| | | | | | | bytes of Inst to 0x0000 for the benefit of the Thumb decoder. llvm-svn: 91496 | |||||
* | Re-enable 91381 with fixes. | Evan Cheng | 2009-12-16 | 3 | -12/+40 | |
| | | | | llvm-svn: 91489 | |||||
* | Every anonymous namespace is different. Caught by clang++. | John McCall | 2009-12-16 | 1 | -4/+0 | |
| | | | | llvm-svn: 91481 | |||||
* | Change indirect-globals to use a dedicated allocIndirectGV. This lets us | Jeffrey Yasskin | 2009-12-15 | 4 | -21/+15 | |
| | | | | | | | | | remove start/finishGVStub and the BufferState helper class from the MachineCodeEmitter interface. It has the side-effect of not setting the indirect global writable and then executable on ARM, but that shouldn't be necessary. llvm-svn: 91464 | |||||
* | Added encoding bits for the Thumb ISA. Initial checkin. | Johnny Chen | 2009-12-15 | 3 | -348/+1219 | |
| | | | | llvm-svn: 91434 | |||||
* | Fix an encoding bug. | Evan Cheng | 2009-12-15 | 1 | -1/+1 | |
| | | | | llvm-svn: 91417 | |||||
* | For fastcc on x86, let ECX be used as a return register after EAX and EDX | Kenneth Uildriks | 2009-12-15 | 1 | -1/+8 | |
| | | | | llvm-svn: 91410 | |||||
* | Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp. | Evan Cheng | 2009-12-15 | 1 | -1/+3 | |
| | | | | llvm-svn: 91405 | |||||
* | Use sbb x, x to materialize carry bit in a GPR. The result is all one's or ↵ | Evan Cheng | 2009-12-15 | 4 | -3/+96 | |
| | | | | | | all zero's. llvm-svn: 91381 | |||||
* | nand atomic requires opposite operand ordering | Jim Grosbach | 2009-12-15 | 1 | -3/+9 | |
| | | | | llvm-svn: 91371 | |||||
* | Fix integer cast code to handle vector types. | Dan Gohman | 2009-12-14 | 1 | -2/+11 | |
| | | | | llvm-svn: 91362 | |||||
* | Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate | Johnny Chen | 2009-12-14 | 1 | -0/+1 | |
| | | | | | | between BR_JTr and STREXD. llvm-svn: 91339 | |||||
* | v6 sync insn copy/paste error | Jim Grosbach | 2009-12-14 | 1 | -1/+1 | |
| | | | | llvm-svn: 91333 | |||||
* | Add ARMv6 memory and sync barrier instructions | Jim Grosbach | 2009-12-14 | 3 | -14/+45 | |
| | | | | llvm-svn: 91329 | |||||
* | Fixed encoding bits typo of ldrexd/strexd. | Johnny Chen | 2009-12-14 | 1 | -2/+2 | |
| | | | | llvm-svn: 91327 | |||||
* | Thumb2 atomic operations | Jim Grosbach | 2009-12-14 | 1 | -44/+83 | |
| | | | | llvm-svn: 91321 | |||||
* | fix an obvious bug found by clang++ and collapse a redundant if. | Chris Lattner | 2009-12-14 | 1 | -7/+6 | |
| | | | | | | | | | | | Here's the diagnostic from clang: /Volumes/Data/dgregor/Projects/llvm/lib/Target/CppBackend/CPPBackend.cpp:989:23: warning: 'gv' is always NULL in this context printConstant(gv); ^ 1 diagnostic generated. llvm-svn: 91318 | |||||
* | correct selection requirements for thumb2 vs. arm versions of the barrier ↵ | Jim Grosbach | 2009-12-14 | 2 | -4/+6 | |
| | | | | | | intrinsics llvm-svn: 91313 | |||||
* | add Thumb2 atomic and memory barrier instruction definitions | Jim Grosbach | 2009-12-14 | 1 | -0/+60 | |
| | | | | llvm-svn: 91310 | |||||
* | whitespace | Jim Grosbach | 2009-12-14 | 1 | -1/+0 | |
| | | | | llvm-svn: 91307 | |||||
* | ARM memory barrier instructions are not predicable | Jim Grosbach | 2009-12-14 | 2 | -3/+20 | |
| | | | | llvm-svn: 91305 | |||||
* | add ldrexd/strexd instructions | Jim Grosbach | 2009-12-14 | 1 | -2/+11 | |
| | | | | llvm-svn: 91284 | |||||
* | Whitespace changes, comment clarification. No functional changes. | Bill Wendling | 2009-12-14 | 1 | -15/+26 | |
| | | | | llvm-svn: 91274 | |||||
* | atomic binary operations up to 32-bits wide. | Jim Grosbach | 2009-12-14 | 1 | -5/+63 | |
| | | | | llvm-svn: 91260 | |||||
* | Do not allow uninitialize access during debug printing | Anton Korobeynikov | 2009-12-13 | 1 | -2/+2 | |
| | | | | llvm-svn: 91232 | |||||
* | More info on this transformation. | Eli Friedman | 2009-12-12 | 1 | -2/+15 | |
| | | | | llvm-svn: 91230 | |||||
* | Remove some stuff that's already implemented. Also, remove the note about | Eli Friedman | 2009-12-12 | 1 | -51/+0 | |
| | | | | | | merging x >u 5 and x <s 20 because it's impossible to implement. llvm-svn: 91228 | |||||
* | Disable r91104 for x86. It causes partial register stall which pessimize ↵ | Evan Cheng | 2009-12-12 | 1 | -12/+12 | |
| | | | | | | code in 32-bit. llvm-svn: 91223 | |||||
* | Implement variable-width shifts. | Anton Korobeynikov | 2009-12-12 | 3 | -7/+170 | |
| | | | | | | No testcase yet - it seems we're exposing generic codegen bugs. llvm-svn: 91221 | |||||
* | Add comment about potential partial register stall. | Evan Cheng | 2009-12-12 | 1 | -0/+5 | |
| | | | | llvm-svn: 91220 | |||||
* | Fix an obvious bug. No test case since LEA16r is not being used. | Evan Cheng | 2009-12-12 | 1 | -1/+1 | |
| | | | | llvm-svn: 91219 | |||||
* | Framework for atomic binary operations. The emitter for the pseudo instructions | Jim Grosbach | 2009-12-12 | 3 | -19/+150 | |
| | | | | | | | just issues an error for the moment. The front end won't yet generate these intrinsics for ARM, so this is behind the scenes until complete. llvm-svn: 91200 | |||||
* | Lower setcc branchless, if this is profitable. | Anton Korobeynikov | 2009-12-11 | 2 | -2/+86 | |
| | | | | | | Based on the patch by Brian Lucas! llvm-svn: 91175 | |||||
* | Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG. | Dan Gohman | 2009-12-11 | 1 | -0/+1 | |
| | | | | llvm-svn: 91158 | |||||
* | memory barrier instructions by definition have side effects. This prevents ↵ | Jim Grosbach | 2009-12-11 | 1 | -1/+1 | |
| | | | | | | the post-RA scheduler from moving them around. llvm-svn: 91150 | |||||
* | Honour setHasCalls() set from isel. | Anton Korobeynikov | 2009-12-11 | 1 | -0/+5 | |
| | | | | | | | This is used in some weird cases like general dynamic TLS model. This fixes PR5723 llvm-svn: 91144 | |||||
* | Store Register Exclusive should leave the source register Inst{3-0} unspecified. | Johnny Chen | 2009-12-11 | 1 | -1/+1 | |
| | | | | llvm-svn: 91143 | |||||
* | Update properties. | Jim Grosbach | 2009-12-11 | 1 | -2/+2 | |
| | | | | llvm-svn: 91140 | |||||
* | Add support to 3-addressify 16-bit instructions. | Evan Cheng | 2009-12-11 | 2 | -88/+135 | |
| | | | | llvm-svn: 91104 | |||||
* | Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in ↵ | Jim Grosbach | 2009-12-11 | 5 | -0/+152 | |
| | | | | | | progress. llvm-svn: 91090 | |||||
* | Add instruction encoding for DMB/DSB | Jim Grosbach | 2009-12-10 | 1 | -3/+11 | |
| | | | | llvm-svn: 91053 | |||||
* | Add memory barrier intrinsic support for ARM. Moving towards adding the ↵ | Jim Grosbach | 2009-12-10 | 3 | -1/+49 | |
| | | | | | | atomic operations intrinsics. llvm-svn: 91003 | |||||
* | Optimize splat of a scalar load into a shuffle of a vector load when it's ↵ | Evan Cheng | 2009-12-09 | 3 | -4/+93 | |
| | | | | | | | | | | | | legal. e.g. vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0> => vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1> iff ptr is 16-byte aligned (or can be made into 16-byte aligned). llvm-svn: 90984 | |||||
* | Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 ↵ | Evan Cheng | 2009-12-09 | 1 | -11/+1 | |
| | | | | | | isl lowering code. llvm-svn: 90925 | |||||
* | Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's ↵ | Evan Cheng | 2009-12-09 | 1 | -1/+1 | |
| | | | | | | primary used by selectdag passes. llvm-svn: 90922 | |||||
* | - Support inline asm 'w' constraint for 128-bit vector types. | Evan Cheng | 2009-12-08 | 2 | -0/+6 | |
| | | | | | | - Also support the 'q' NEON registers asm code. llvm-svn: 90894 |