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* Expand rotate instructions on sparcv9 as well.Roman Divacky2013-11-121-0/+2
| | | | llvm-svn: 194500
* Simplify operand folding when rematerializing a load.Andrew Trick2013-11-121-1/+6
| | | | | | | | | | | | We already know how to fold a reload from a frameindex without analyzing the load instruction. Generalize this to handle any frameindex load. This streamlines the logic for rematerializing loads from stack arguments. As a side effect, it allows stackmaps to record a stack argument location without spilling it. Verified no effect on codegen for llvm test-suite. llvm-svn: 194497
* R600: Reenable llvm.R600.load.input/interp.input for compatibilityVincent Lejeune2013-11-122-0/+47
| | | | llvm-svn: 194484
* [mips][msa] Enable inlinse assembly for MSA.Daniel Sanders2013-11-122-9/+51
| | | | | | | | | | | | | | Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
* [mips][msa] Fix buildbot failures caused by an unused variable when ↵Daniel Sanders2013-11-121-2/+1
| | | | | | assertions are disabled. llvm-svn: 194472
* [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. ↵Daniel Sanders2013-11-129-38/+161
| | | | | | not intrinsics) llvm-svn: 194471
* [ARM] Add support for FP_HP_extension build attributeBradley Smith2013-11-122-1/+7
| | | | llvm-svn: 194470
* [mips][msa] Added support for matching bset, bseti, bneg, and bnegi from ↵Daniel Sanders2013-11-122-70/+216
| | | | | | normal IR (i.e. not intrinsics) llvm-svn: 194469
* XCore target: fix bug in aligning 'byval i8*' on the stackRobert Lytton2013-11-121-1/+1
| | | | llvm-svn: 194466
* Add XCore support for ATOMIC_FENCE.Robert Lytton2013-11-123-1/+25
| | | | | | | | | | ATOMIC_FENCE is lowered to a compiler barrier which is codegen only. There is no need to emit an instructions since the XCore provides sequential consistency. Original patch by Richard Osborne llvm-svn: 194464
* XCore target: return error for unsupported alignmentRobert Lytton2013-11-121-0/+4
| | | | llvm-svn: 194463
* R600/SI: Change formatting of printed registers.Matt Arsenault2013-11-122-2/+64
| | | | | | | | | | | | | | | | | | | | | | | Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. llvm-svn: 194443
* Change the default branch instruction to be the 16 bit variety for mips16.Reed Kotler2013-11-123-5/+26
| | | | | | | | | | | This has no material effect at this time since we don't have a direct object emitter for mips16 and the assembler can't tell them apart. I place a comment "16 bit inst" for those so that I can tell them apart in the output. The constant island pass has only been minimally changed to allow this. More complete branch work is forthcoming but this is the first step. llvm-svn: 194442
* Lower X86::MORESTACK_RET and X86::MORESTACK_RET_RESTORE_R10 inLang Hames2013-11-111-12/+12
| | | | | | | | | | | | | | X86AsmPrinter::EmitInstruction, rather than X86MCInstLower::Lower. The aim is to improve the reusability of the X86MCInstLower class by making it more function-like. The X86::MORESTACK_RET_RESTORE_R10 pseudo broke the function model by emitting an extra instruction to the MCStreamer attached to the AsmPrinter. The patch should have no impact on generated code. llvm-svn: 194431
* Fix the recently added anyregcc convention to handle spilled operands.Andrew Trick2013-11-111-1/+10
| | | | | | | | | | | | Fixes <rdar://15432754> [JS] Assertion: "Folded a def to a non-store!" The primary purpose of anyregcc is to prevent a patchpoint's call arguments and return value from being spilled. They must be available in a register, although the calling convention does not pin the register. It's up to the front end to avoid using this convention for calls with more arguments than allocatable registers. llvm-svn: 194428
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-114-41/+39
| | | | llvm-svn: 194425
* [mips] Partially revert r193641. Stack alignment should not be determined byAkira Hatanaka2013-11-111-1/+1
| | | | | | | the floating point register mode. llvm-svn: 194423
* [ARM] Add support for MVFR2 which is new in ARMv8Artyom Skrobov2013-11-112-0/+3
| | | | llvm-svn: 194416
* [NVPTX] Properly handle bitcast ConstantExpr when checking for the alignment ↵Justin Holewinski2013-11-111-13/+38
| | | | | | of function parameters llvm-svn: 194410
* [NVPTX] Fix logic error in loading vector parameters of more than 4 componentsJustin Holewinski2013-11-111-1/+1
| | | | llvm-svn: 194409
* [AArch64] The shift right/left and insert immediate builtins expect 3Chad Rosier2013-11-111-10/+21
| | | | | | source operands, a vector, an element to insert, and a shift amount. llvm-svn: 194406
* [AArch64] Add support for NEON scalar floating-point convert to fixed-point ↵Chad Rosier2013-11-111-3/+25
| | | | | | instructions. llvm-svn: 194394
* Add PPC option for full register names in asmHal Finkel2013-11-111-0/+10
| | | | | | | | | | | | | | | | | | | | | On non-Darwin PPC systems, we currently strip off the register name prefix prior to instruction printing. So instead of something like this: mr r3, r4 we print this: mr 3, 4 The first form is the default on Darwin, and is understood by binutils, but not yet understood by our integrated assembler. Once our integrated-as understands full register names as well, this temporary option will be replaced by tying this functionality to the verbose-asm option. The numeric-only form is compatible with legacy assemblers and tools, and is also gcc's default on most PPC systems. On the other hand, it is harder to read, and there are some analysis tools that expect full register names. llvm-svn: 194384
* [NVPTX] Blacklist TailDuplicate passJustin Holewinski2013-11-111-0/+1
| | | | | | | | This causes issues with virtual registers. We will likely need to fix TailDuplicate in the future, or introduce a new version that plays nicely with vregs. llvm-svn: 194373
* AArch64: refactor vector list creation to be more uniformTim Northover2013-11-111-101/+55
| | | | | | | | | | | Instructions taking a vector list (e.g. "ld2 {v0.2d, v1.d2}, [x0]") need a special register-class to deal with the constraints, and C++ code to support selection. However, that C++ code can be made reasonably uniform to simplify the selection process. Hence this patch. No functionality change, so no tests. llvm-svn: 194361
* Make method staticMatt Arsenault2013-11-102-2/+2
| | | | llvm-svn: 194340
* Fix missing C++ mode commentMatt Arsenault2013-11-101-1/+1
| | | | llvm-svn: 194339
* Mostly finish up constant islands port for Mips for load constants.Reed Kotler2013-11-101-3/+20
| | | | | | | Still need to finish the branch part. Still lots more review of the code, clean up and testing. llvm-svn: 194337
* Remove some unnecessary temporary strings.Benjamin Kramer2013-11-092-6/+5
| | | | llvm-svn: 194335
* [arm] Refine ARMBuildAttrs.h.Logan Chien2013-11-091-6/+8
| | | | | | | | This commit cleans up some comments in ARMBuildAttrs.h. Besides, this commit fixes an error related to AllowWMMXv1 and AllowWMMXv2 (although they are not used currently.) llvm-svn: 194327
* [mips] Make sure there is a chain edge dependency between loads that readAkira Hatanaka2013-11-091-3/+5
| | | | | | | | | formal arguments on the stack and stores created afterwards. We need this to ensure tail call optimized function calls do not write over the argument area of the stack before it is read out. llvm-svn: 194309
* [Stackmap] Materialize the jump address within the patchpoint noop slide.Juergen Ributzka2013-11-093-3/+29
| | | | | | | | | | | | | | | This patch moves the jump address materialization inside the noop slide. This enables patching of the materialization itself or its complete removal. This patch also adds the ability to define scratch registers that can be used safely by the code called from the patchpoint intrinsic. At least one scratch register is required, because that one is used for the materialization of the jump address. This patch depends on D2009. Differential Revision: http://llvm-reviews.chandlerc.com/D2074 Reviewed by Andy llvm-svn: 194306
* [Stackmap] Add AnyReg calling convention support for patchpoint intrinsic.Juergen Ributzka2013-11-087-10/+101
| | | | | | | | | | | | | | The idea of the AnyReg Calling Convention is to provide the call arguments in registers, but not to force them to be placed in a paticular order into a specified set of registers. Instead it is up tp the register allocator to assign any register as it sees fit. The same applies to the return value (if applicable). Differential Revision: http://llvm-reviews.chandlerc.com/D2009 Reviewed by Andy llvm-svn: 194293
* X86: Assembly files with .cfi_cfa_def shouldn't hit llvm_unreachable()Jim Grosbach2013-11-081-1/+3
| | | | | | | | | | On darwin, when trying to create compact unwind info, a .cfi_cfa_def directive would case an llvm_unreachable() to be hit. Back off when we see this directive and generate the regular DWARF style eh_frame. rdar://15406518 llvm-svn: 194285
* Make PrintAsmOperand call to the superclass to handle 'n' and 'c' operand ↵Richard Barton2013-11-081-6/+2
| | | | | | modifiers. llvm-svn: 194270
* ARM: fold prologue/epilogue sp updates into push/pop for code sizeTim Northover2013-11-084-32/+166
| | | | | | | | | | | | | | | | | | ARM prologues usually look like: push {r7, lr} sub sp, sp, #4 If code size is extremely important, this can be optimised to the single instruction: push {r6, r7, lr} where we don't actually care about the contents of r6, but pushing it subtracts 4 from sp as a side effect. This should implement such a conversion, predicated on the "minsize" function attribute (-Oz) since I've yet to find any code it actually makes faster. llvm-svn: 194264
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-081-8/+21
| | | | | | ARMv8 (Thumb encodings) llvm-svn: 194263
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-082-9/+24
| | | | | | ARMv8 (ARM encodings) llvm-svn: 194261
* [mips][msa] Update encoding of LDI instruction.Matheus Almeida2013-11-081-4/+4
| | | | | | The encoding was updated in MSA r1.07. llvm-svn: 194255
* [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 ↵Artyom Skrobov2013-11-081-2/+3
| | | | | | as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings llvm-svn: 194253
* Support for microMIPS trap instructions 1.Zoran Jovanovic2013-11-074-8/+32
| | | | llvm-svn: 194205
* Disable some code that is causing some warnings. It's in the processReed Kotler2013-11-071-3/+2
| | | | | | | | of being converted and this path is not relevant to anything at this time so I have just disabled it for a few days while I'm at the LLVM conference and don't have time to complete it or properly fix it. llvm-svn: 194201
* R600: Fix LowerUDIVREMVincent Lejeune2013-11-061-5/+5
| | | | llvm-svn: 194153
* [AArch64] Remove NEON from "generic" CPU target.Amara Emerson2013-11-061-2/+1
| | | | | | | We can change this back when NEON support is complete and ready to become enabled by default. llvm-svn: 194152
* [SystemZ] Handle vectors in getSetCCResultTypeRichard Sandiford2013-11-062-5/+8
| | | | | | | I don't have a standalone testcase for this, but it should allow r193676 to be reapplied. llvm-svn: 194148
* Implement gpword directive for mips, test case added. Stype changes using ↵Vladimir Medic2013-11-061-299/+313
| | | | | | clang-format are also included. llvm-svn: 194145
* [llvm-c] Improve TargetMachine bindingsPeter Zotov2013-11-061-0/+39
| | | | | | Original patch by Chris Wailes llvm-svn: 194143
* Fix definition for Mips16 pc relative load word instructions.Reed Kotler2013-11-061-5/+3
| | | | llvm-svn: 194126
* Implement AArch64 Neon instruction set Perm.Jiangning Liu2013-11-062-0/+347
| | | | llvm-svn: 194123
* Implement AArch64 Neon instruction set Bitwise Extract.Jiangning Liu2013-11-066-100/+203
| | | | llvm-svn: 194118
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