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* Try to fix an SDAG dependence issue with sretReid Kleckner2014-05-122-18/+23
| | | | | | | | | | | | | | | | r208453 added support for having sret on the second parameter. In that change, the code for copying sret into a virtual register was hoisted into the loop that lowers formal parameters. This caused a "Wrong topological sorting" assertion failure during scheduling when a parameter is passed in memory. This change undoes that by creating a second loop that deals with sret. I'm worried that this fix is incomplete. I don't fully understand the dependence issues. However, with this change we produce the same DAGs we used to produce, so if they are broken, they are just as broken as they have always been. llvm-svn: 208637
* Use cast<> for unchecked useMatt Arsenault2014-05-121-1/+1
| | | | llvm-svn: 208627
* Add support bswap16 to/from memory compiling to rev16 on ARM/ThumbLouis Gerbarg2014-05-122-0/+17
| | | | | | | | | | | The current patterns for REV16 misses mostn __builtin_bswap16() due to legalization promoting the operands to from load/stores toi32s and then truncing/extending them. This patch adds new patterns that catch the resultant DAGs and codegens them to rev16 instructions. Tests included. rdar://15353652 llvm-svn: 208620
* Use cast<> for unchecked useMatt Arsenault2014-05-121-2/+2
| | | | llvm-svn: 208618
* Use range forMatt Arsenault2014-05-122-6/+4
| | | | llvm-svn: 208617
* TableGen: use PrintMethods to print more aliasesTim Northover2014-05-1212-41/+86
| | | | llvm-svn: 208607
* AArch64/ARM64: use InstAliases for NEON logical (imm) instructions.Tim Northover2014-05-122-72/+67
| | | | llvm-svn: 208606
* AArch64/ARM64: implement "mov $Rd, $Imm" aliases in TableGen.Tim Northover2014-05-123-58/+94
| | | | | | | | This is a slightly different approach to AArch64 (the base instruction definitions aren't quite right for that to work), but achieves the same thing and reduces C++ hackery in AsmParser. llvm-svn: 208605
* R600: Add mul24 intrinsicsMatt Arsenault2014-05-123-4/+10
| | | | llvm-svn: 208604
* Revert: r208582 - [mips][mips64r6] Add sel.s and sel.dDaniel Sanders2014-05-122-52/+4
| | | | | | Accidentally committed an unreviewed patch. Reverted it. llvm-svn: 208583
* [mips][mips64r6] Add sel.s and sel.dDaniel Sanders2014-05-122-4/+52
| | | | | | | | | | | | | Summary: Also use named constants for common opcode fields. Depends on D3669 Reviewers: jkolek, vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D3670 llvm-svn: 208582
* [mips][mips64r6] Add d?div, d?mod, d?divu, d?moduDaniel Sanders2014-05-122-8/+32
| | | | | | | | | | | | Summary: Depends on D3668 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3669 llvm-svn: 208579
* [mips][mips64r6] Added mul/mulu/muh/muhuDaniel Sanders2014-05-125-9/+115
| | | | | | | | | | | | Summary: The 'mul' line of the test is temporarily commented out because it currently matches the MIPS32 mul instead of the MIPS32r6 mul. This line will be uncommented when we disable the MIPS32 mul on MIPS32r6. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3668 llvm-svn: 208576
* Silencing an MSVC warning about not all control paths returning a value ↵Aaron Ballman2014-05-121-0/+1
| | | | | | (even though the switch is fully covered). No functional change. llvm-svn: 208565
* ARM64: remove dead validation code from the AsmParser.Tim Northover2014-05-121-198/+0
| | | | | | | If this code triggers, any immediate has already been validated so it can't possibly trigger a diagnostic. llvm-svn: 208564
* ARM64: merge "extend" and "shift" addressing-mode enums.Tim Northover2014-05-126-330/+241
| | | | | | | | In terms of assembly, these have too much overlap to be neatly modelled as disjoint classes: in many cases "lsl" is an acceptable alternative to either "uxtw" or "uxtx". llvm-svn: 208563
* Remove an always true argument.Rafael Espindola2014-05-121-1/+1
| | | | llvm-svn: 208557
* X86: Make sure that we have SSE4.1 before we generate insertps nodes.Benjamin Kramer2014-05-121-1/+1
| | | | | | PR19721. llvm-svn: 208552
* [mips] Marked up instructions added in MIPS32 and tested that IAS for ↵Daniel Sanders2014-05-121-8/+8
| | | | | | | | | | | | | | | | -mcpu=mips2 does not accept them Summary: To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are explicitly tested. Depends on D3695 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3696 llvm-svn: 208549
* Remove MCUseCFI from TargetMachine.Rafael Espindola2014-05-121-1/+0
| | | | | | It was always true. llvm-svn: 208547
* [mips] Marked up instructions added in MIPS-V and tested that IAS for ↵Daniel Sanders2014-05-126-9/+23
| | | | | | | | | | | | | | | | | | | | | | -mcpu=mips[1234] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-V that was available in MIPS32R2 Most of these instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. It happens because many of the MIPS V instructions have not been implemented. Depends on D3694 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3695 llvm-svn: 208546
* [mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64Daniel Sanders2014-05-127-25/+17
| | | | | | | | | | | | | | | | | | | | | Summary: DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no effect on the CodeGen tests since expansion of i64 prevented their use anyway. The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as well. This is not a functional change since DCLZ is still prohibited by being a MIPS64 instruction (MIPS16 is only compatible with MIPS32). No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3694 llvm-svn: 208544
* [mips] Fold FeatureSEInReg into FeatureMips32r2Daniel Sanders2014-05-127-26/+20
| | | | | | | | | | | | Summary: No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3693 llvm-svn: 208543
* [mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2Daniel Sanders2014-05-127-23/+14
| | | | | | | | | | | | | | | | | Summary: dsbh and dshd are not available on Mips32r2. No codegen test changes required since expansion of i64 prevented the use of these instructions anyway. Depends on D3690 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3692 llvm-svn: 208542
* [mips] Replace FeatureFPIdx with FeatureMips4_32r2Daniel Sanders2014-05-126-31/+40
| | | | | | | | | | | | | | | | | Summary: No functional change. The minor change to the MIPS16 code is in preparation for a patch that will handle 32-bit FPIdx instructions separately to 64-bit (because they were added in different revisions) Depends on D3677 Reviewers: rkotler, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3690 llvm-svn: 208541
* [ARM64] Add proper bounds checking/diagnostics to logical shiftsBradley Smith2014-05-123-22/+43
| | | | llvm-svn: 208540
* ARM: Implement big endian bit-conversion for NEON typeChristian Pirker2014-05-123-56/+142
| | | | llvm-svn: 208538
* X86ISelLowering.cpp:LowerINTRINSIC_W_CHAIN(): Prune impossible "default:" ↵NAKAMURA Takumi2014-05-121-3/+0
| | | | | | [-Wcovered-switch-default] llvm-svn: 208533
* [ARM64] Add diagnostics for bitfield extract/insert instructionsBradley Smith2014-05-121-19/+54
| | | | | | | | Unfortunately, since ARM64 models all these instructions as aliases, the checks need to be done at the time the alias is seen rather than during instruction validation as AArch64 does it. llvm-svn: 208529
* [ARM64] Correct more bounds checks/diagnostics for arithmetic shift operandsBradley Smith2014-05-122-10/+18
| | | | llvm-svn: 208528
* [ARM64] Move register/register MOV handling into tablegen and improve ↵Bradley Smith2014-05-124-54/+26
| | | | | | diagnostics llvm-svn: 208527
* Fixed compilation issueElena Demikhovsky2014-05-121-0/+1
| | | | llvm-svn: 208524
* AVX-512: changes in intrinsicsElena Demikhovsky2014-05-124-192/+231
| | | | | | | | | 1) Changed gather and scatter intrinsics. Now they are aligned with GCC built-ins. There is no more non-masked form. Masked intrinsic receives -1 if all lanes are executed. 2) I changed the function that works with intrinsics inside X86ISelLowering.cpp. I put all intrinsics in one table. I did it for INTRINSICS_W_CHAIN and plan to put all intrinsics from WO_CHAIN set to the same table in order to avoid the long-long "switch". (I wanted to use static map initialization that allowed by C++11 but I wasn't able to compile it on VS2012). 3) I added gather/scatter prefetch intrinsics. 4) I fixed MRMm encoding for masked instructions. llvm-svn: 208522
* Fix return before elseMatt Arsenault2014-05-111-18/+18
| | | | llvm-svn: 208510
* [PowerPC] Add global named register supportHal Finkel2014-05-112-0/+27
| | | | | | | Support for the intrinsics that read from and write to global named registers is added for r1, r2 and r13 (depending on the subtarget). llvm-svn: 208509
* Pass the value type to TLI::getRegisterByNameHal Finkel2014-05-118-8/+12
| | | | | | | | | | | | | We must validate the value type in TLI::getRegisterByName, because if we don't and the wrong type was used with the IR intrinsic, then we'll assert (because we won't be able to find a valid register class with which to construct the requested copy operation). For PPC64, additionally, the type information is necessary to decide between the 64-bit register and the 32-bit subregister. No functionality change. llvm-svn: 208508
* Add 'override' to getRegisterByName in *ISelLowering.hHal Finkel2014-05-114-4/+4
| | | | | | No functionality change intended. llvm-svn: 208507
* [PowerPC] On PPC32, 128-bit shifts might be runtime callsHal Finkel2014-05-111-0/+8
| | | | | | | | | | | The counter-loops formation pass needs to know what operations might be function calls (because they can't appear in counter-based loops). On PPC32, 128-bit shifts might be runtime calls (even though you can't use __int128 on PPC32, it seems that SROA might form them). Fixes PR19709. llvm-svn: 208501
* Fixed a bug when lowering build_vector (PR19694)Filipe Cabecinhas2014-05-111-3/+8
| | | | | | | | When lowering build_vector to an insertps, we would still lower it, even if the source vectors weren't v4x32. This would break on avx if the source was a v8x32. We now check the type of the source vectors. llvm-svn: 208487
* R600/SI: Fold fabs/fneg into src input modifierVincent Lejeune2014-05-101-2/+31
| | | | llvm-svn: 208480
* R600/SI: Prettier display of input modifiersVincent Lejeune2014-05-107-38/+77
| | | | llvm-svn: 208479
* R600/SI: Use pseudo instruction for fabs/clamp/fnegVincent Lejeune2014-05-102-4/+74
| | | | llvm-svn: 208478
* ARM64: fix SELECT_CC lowering in absence of NaNs.Tim Northover2014-05-101-8/+9
| | | | | | | | | | We were swapping the true & false results while testing for FMAX/FMIN, but not putting them back to the original state if the later checks failed. Should fix PR19700. llvm-svn: 208469
* Revert "[ms-cxxabi] Add a new calling convention that swaps 'this' and 'sret'"Reid Kleckner2014-05-092-37/+0
| | | | | | | | | | | | | | This reverts commit r200561. This calling convention was an attempt to match the MSVC C++ ABI for methods that return structures by value. This solution didn't scale, because it would have required splitting every CC available on Windows into two: one for methods and one for free functions. Now that we can put sret on the second arg (r208453), and Clang does that (r208458), revert this hack. llvm-svn: 208459
* Allow sret on the second parameter as well as the firstReid Kleckner2014-05-093-30/+34
| | | | | | | | | | | | | | | | | | | | | | | | | MSVC always places the implicit sret parameter after the implicit this parameter of instance methods. We used to handle this for x86_thiscallcc by allocating the sret parameter on the stack and leaving the this pointer in ecx, but that doesn't handle alternative calling conventions like cdecl, stdcall, fastcall, or the win64 convention. Instead, change the verifier to allow sret on the second parameter. This also requires changing the Mips and X86 backends to return the argument with the sret parameter, instead of assuming that the sret parameter comes first. The Sparc backend also returns sret parameters in a register, but I wasn't able to update it to handle secondary sret parameters. It currently calls report_fatal_error if you feed it an sret in the second parameter. Reviewers: rafael.espindola, majnemer Differential Revision: http://reviews.llvm.org/D3617 llvm-svn: 208453
* Fix broken buildJonathan Roelofs2014-05-091-1/+1
| | | | | | ARM64 backend was missing a required_library entry. llvm-svn: 208437
* Add custom lowering for add/sub with overflow intrinsics to ARMLouis Gerbarg2014-05-092-0/+97
| | | | | | | | | | | | | This patch adds support to ARM for custom lowering of the llvm.{u|s}add.with.overflow.i32 intrinsics for i32/i64. This is particularly useful for handling idiomatic saturating math functions as generated by InstCombineCompare. Test cases included. rdar://14853450 llvm-svn: 208435
* R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructionsTom Stellard2014-05-091-4/+35
| | | | llvm-svn: 208432
* R600/SI: Fix SMRD pattern for offsets > 32 bitsTom Stellard2014-05-092-7/+6
| | | | | | We were dropping the high bits of 64-bit immediate offsets. llvm-svn: 208431
* R600: Expand i64 SELECT_CCTom Stellard2014-05-091-0/+2
| | | | llvm-svn: 208430
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