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* Update the datalayout string for ppc64LE.Will Schmidt2014-03-121-2/+7
| | | | | | Update the datalayout string for ppc64LE. llvm-svn: 203664
* [mips][fp64] Add an implicit def to MTHC1 claiming that it reads the lower ↵Daniel Sanders2014-03-121-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 32-bits of 64-bit FPR Summary: This is a white lie to workaround a widespread bug in the -mfp64 implementation. The problem is that none of the 32-bit fpu ops mention the fact that they clobber the upper 32-bits of the 64-bit FPR. This allows MTHC1 to be scheduled on the wrong side of most 32-bit FPU ops, particularly MTC1. Fixing that requires a major overhaul of the FPU implementation which can't be done right now due to time constraints. The testcase is SingleSource/Benchmarks/Misc/oourafft.c when given TARGET_CFLAGS='-mips32r2 mfp64 -mmsa'. Also correct the comment added in r203464 to indicate that two instructions were affected. Reviewers: matheusalmeida, jacksprat Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3029 llvm-svn: 203659
* [mips] BSEL's and BINS[RL] operands are reversed compared to the vselect ↵Daniel Sanders2014-03-123-17/+42
| | | | | | | | | | | | | | | | | | | | | | | node used in the pattern. Summary: Correct the match patterns and the lowerings that made the CodeGen tests pass despite the mistakes. The original testcase that discovered the problem was SingleSource/UnitTests/SignlessType/factor.c in test-suite. During review, we also found that some of the existing CodeGen tests were incorrect and fixed them: * bitwise.ll: In bsel_v16i8 the IfSet/IfClear were reversed because bsel and bmnz have different operand orders and the test didn't correctly account for this. bmnz goes 'IfClear, IfSet, CondMask', while bsel goes 'CondMask, IfClear, IfSet'. * vec.ll: In the cases where a bsel is emitted as a bmnz (they are the same operation with a different input tied to the result) the operands were in the wrong order. * compare.ll and compare_float.ll: The bsel operand order was correct for a greater-than comparison, but a greater-than comparison instruction doesn't exist. Lowering this operation inverts the condition so the IfSet/IfClear need to be swapped to match. The differences between BSEL, BMNZ, and BMZ and how they map to/from vselect are rather confusing. I've therefore added a note to MSA.txt to explain this in a single place in addition to the comments that explain each case. Reviewers: matheusalmeida, jacksprat Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3028 llvm-svn: 203657
* ARM: correct Dwarf output for non-contiguous VFP saves.Tim Northover2014-03-121-0/+9
| | | | | | | | | | | | | | | | | | When the list of VFP registers to be saved was non-contiguous (so multiple vpush/vpop instructions were needed) these were being ordered oddly, as in: vpush {d8, d9} vpush {d11} This led to the layout in memory being [d11, d8, d9] which is ugly and doesn't match the CFI_INSTRUCTIONs we're generating either (so Dwarf info would be broken). This switches the order of vpush/vpop (in both prologue and epilogue, obviously) so that the Dwarf locations are correct again. rdar://problem/16264856 llvm-svn: 203655
* Replace '#include ValueTypes.h' with forward declarations.Patrik Hagglund2014-03-129-8/+6
| | | | | | | In some cases the include is pushed "downstream" (or removed if unused). llvm-svn: 203644
* [ARM] Use DWARF register numbers for CFI directives in ELF assemblyHans Wennborg2014-03-121-0/+3
| | | | | | | | | | | | | | It seems gas can't handle CFI directives with VFP register names ("d12", etc.). This broke us trying to build Chromium for Android after 201423. A gas bug has been filed: https://sourceware.org/bugzilla/show_bug.cgi?id=16694 compnerd suggested making this conditional on whether we're using the integrated assembler or not. I'll look into that in a follow-up patch. Differential Revision: http://llvm-reviews.chandlerc.com/D3049 llvm-svn: 203635
* [mips] Implement NaCl sandboxing of function calls:Sasa Stankovic2014-03-111-2/+56
| | | | | | | | | * Add masking instructions before indirect calls (in MC layer). * Align call + branch delay to the bundle end (in MC layer). Differential Revision: http://llvm-reviews.chandlerc.com/D3032 llvm-svn: 203606
* Simplify a really complicated check for Arch == X86_64.Rafael Espindola2014-03-111-1/+0
| | | | | | | | | | | | The function hasReliableSymbolDifference had exactly one use in the MachO writer. It is also only true for X86_64. In fact, the comments refers to "Darwin x86_64" and everything else, so this makes the code match the comment. If this is to be abstracted again, it should be a property of TargetObjectWriter, like useAggressiveSymbolFolding. llvm-svn: 203605
* Range-ify a loop.Owen Anderson2014-03-111-4/+1
| | | | llvm-svn: 203590
* X86: Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059)Hans Wennborg2014-03-111-4/+20
| | | | | | | | | This fixes the bug where we would bitcast the 64-bit floating point result of cmpneqsd to a 64-bit integer even on 32-bit targets. Differential Revision: http://llvm-reviews.chandlerc.com/D3009 llvm-svn: 203581
* ARM: honour -f{no-,}optimize-sibling-callsSaleem Abdulrasool2014-03-111-2/+4
| | | | | | | | | | | Use the options in the ARMISelLowering to control whether tail calls are optimised or not. Previously, this option was entirely ignored on the ARM target and only honoured on x86. This option is mostly useful in profiling scenarios. The default remains that tail call optimisations will be applied. llvm-svn: 203577
* ARM: remove ancient -arm-tail-calls optionSaleem Abdulrasool2014-03-111-8/+2
| | | | | | | | This option is from 2010, designed to work around a linker issue on Darwin for ARM. According to grosbach this is no longer an issue and this option can safely be removed. llvm-svn: 203576
* ARM: enable tail call optimisation on Thumb 2Saleem Abdulrasool2014-03-111-1/+3
| | | | | | | | | | | | Tail call optimisation was previously disabled on all targets other than iOS5.0+. This enables the tail call optimisation on all Thumb 2 capable platforms. The test adjustments are to remove the IR hint "tail" to function invocation. The tests were designed assuming that tail call optimisations would not kick in which no longer holds true. llvm-svn: 203575
* ARM: simplify EmitAtomicBinary64Tim Northover2014-03-113-34/+19
| | | | | | | | | ATOMIC_STORE operations always get here as a lowered ATOMIC_SWAP, so there's no need for any code to handle them specially. There should be no functionality change so no tests. llvm-svn: 203567
* IR: add a second ordering operand to cmpxhg for failureTim Northover2014-03-113-6/+11
| | | | | | | | | | | | | | | The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 llvm-svn: 203559
* R600: Calculate store mask instead of using switch.Matt Arsenault2014-03-111-17/+3
| | | | llvm-svn: 203527
* X86: Enable ISel of 16-bit MOVBE instructions.Jim Grosbach2014-03-112-1/+9
| | | | | | | | | | | | | | | | | When the MOVBE instructions are available, use them for 16-bit endian swapping as well as for 32 and 64 bit. The patterns were already present on the instructions, but weren't being matched because the operation was unconditionally marked to 'Expand.' Change that to be conditional on whether the MOVBE instructions are available. Use 'rolw' to implement the in-register version (32 and 64 bit have the dedicated 'bswap' instruction for that). Patch by Louis Gerbarg <lgg@apple.com>. rdar://15479984 llvm-svn: 203524
* Remove incomplete commentMatt Arsenault2014-03-111-2/+0
| | | | llvm-svn: 203518
* Move trivial getter into header.Matt Arsenault2014-03-112-7/+4
| | | | llvm-svn: 203517
* Use .data() instead of &x[0]Matt Arsenault2014-03-111-2/+2
| | | | llvm-svn: 203516
* Fix indentationMatt Arsenault2014-03-111-9/+8
| | | | llvm-svn: 203515
* [mips] Implement NaCl sandboxing of loads, stores and SP changes:Sasa Stankovic2014-03-103-5/+123
| | | | | | | | | | * Add masking instructions before loads and stores (in MC layer). * Add masking instructions after SP changes (in MC layer). * Forbid loads, stores and SP changes in delay slots (in MI layer). Differential Revision: http://llvm-reviews.chandlerc.com/D2904 llvm-svn: 203484
* Make sure NVPTX doesn't emit symbol names that aren't valid in PTX.Eli Bendersky2014-03-102-16/+48
| | | | | | | | | | NVPTX, like the other backends, relies on generic symbol name sanitizing done by MCSymbol. However, the ptxas assembler is more stringent and disallows some additional characters in symbol names. See PR19099 for more details. llvm-svn: 203483
* Fix regression with -O0 for mips .Reed Kotler2014-03-101-0/+12
| | | | llvm-svn: 203469
* [mips][fp64] Add an implicit def to MFHC1 claiming that it reads the lower ↵Daniel Sanders2014-03-101-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 32-bits of 64-bit FPR Summary: This is a white lie to workaround a widespread bug in the -mfp64 implementation. The problem is that none of the 32-bit fpu ops mention the fact that they clobber the upper 32-bits of the 64-bit FPR. This allows MFHC1 to be scheduled on the wrong side of most 32-bit FPU ops. Fixing that requires a major overhaul of the FPU implementation which can't be done right now due to time constraints. MFHC1 is one of two affected instructions. These instructions are the only FPU instructions that don't read or write the lower 32-bits. We therefore pretend that it reads the bottom 32-bits to artificially create a dependency and prevent the scheduler changing the behaviour of the code. The other instruction is MTHC1 which will be fixed once I've have found a failing test case for it. The testcase is test-suite/SingleSource/UnitTests/Vector/simple.c when given TARGET_CFLAGS="-mips32r2 -mfp64 -mmsa". Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2966 llvm-svn: 203464
* [mips] Assembly parser must invoke the target streamer to handle .set ↵Matheus Almeida2014-03-101-0/+1
| | | | | | reorder macro. llvm-svn: 203459
* AArch64: fix LowerCONCAT_VECTORS for new CodeGen.Tim Northover2014-03-101-10/+11
| | | | | | | | | | | | | | | The function was making too many assumptions about its input: 1. The NEON_VDUP optimisation was far too aggressive, assuming (I think) that the input would always be BUILD_VECTOR. 2. We were treating most unknown concats as legal (by returning Op rather than SDValue()). I think only concats of pairs of vectors are actually legal. http://llvm.org/PR19094 llvm-svn: 203450
* [C++11] Remove 'virtual' keyword from methods marked with 'override' keyword.Craig Topper2014-03-104-68/+64
| | | | llvm-svn: 203444
* [AArch64] Fix a use of uninitialized memory introduced in r203125,Chandler Carruth2014-03-101-3/+3
| | | | | | | and caught by the MSan bootstrap build bot. This should hopefully get the bot green at long last. llvm-svn: 203441
* De-virtualize a method since it doesn't override anything and isn't ↵Craig Topper2014-03-101-1/+1
| | | | | | overridden itself. llvm-svn: 203440
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-1010-115/+114
| | | | | | class. llvm-svn: 203439
* [TTI] There is actually no realistic way to pop TTI implementations offChandler Carruth2014-03-106-22/+0
| | | | | | | | | | | | | | the stack of the analysis group because they are all immutable passes. This is made clear by Craig's recent work to use override systematically -- we weren't overriding anything for 'finalizePass' because there is no such thing. This is kind of a lame restriction on the API -- we can no longer push and pop things, we just set up the stack and run. However, I'm not invested in building some better solution on top of the existing (terrifying) immutable pass and legacy pass manager. llvm-svn: 203437
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-1031-414/+407
| | | | | | class. llvm-svn: 203433
* [Sparc] Add support for decoding 'swap' instruction.Venkatraman Govindaraju2014-03-092-1/+37
| | | | llvm-svn: 203424
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-0911-63/+60
| | | | | | class. llvm-svn: 203418
* Revert r203230, "CodeGenPrep: sink extends of illegal types into use block."NAKAMURA Takumi2014-03-091-0/+48
| | | | | | It choked i686 stage2. llvm-svn: 203386
* De-virtualize some methods since they don't override anything.Craig Topper2014-03-091-13/+13
| | | | llvm-svn: 203379
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-0918-288/+291
| | | | | | class. llvm-svn: 203378
* [C++11] Add range based accessors for the Use-Def chain of a Value.Chandler Carruth2014-03-096-46/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This requires a number of steps. 1) Move value_use_iterator into the Value class as an implementation detail 2) Change it to actually be a *Use* iterator rather than a *User* iterator. 3) Add an adaptor which is a User iterator that always looks through the Use to the User. 4) Wrap these in Value::use_iterator and Value::user_iterator typedefs. 5) Add the range adaptors as Value::uses() and Value::users(). 6) Update *all* of the callers to correctly distinguish between whether they wanted a use_iterator (and to explicitly dig out the User when needed), or a user_iterator which makes the Use itself totally opaque. Because #6 requires churning essentially everything that walked the Use-Def chains, I went ahead and added all of the range adaptors and switched them to range-based loops where appropriate. Also because the renaming requires at least churning every line of code, it didn't make any sense to split these up into multiple commits -- all of which would touch all of the same lies of code. The result is still not quite optimal. The Value::use_iterator is a nice regular iterator, but Value::user_iterator is an iterator over User*s rather than over the User objects themselves. As a consequence, it fits a bit awkwardly into the range-based world and it has the weird extra-dereferencing 'operator->' that so many of our iterators have. I think this could be fixed by providing something which transforms a range of T&s into a range of T*s, but that *can* be separated into another patch, and it isn't yet 100% clear whether this is the right move. However, this change gets us most of the benefit and cleans up a substantial amount of code around Use and User. =] llvm-svn: 203364
* Change else if => if after return, after r203265Duncan P. N. Exon Smith2014-03-081-8/+9
| | | | llvm-svn: 203347
* Range-ify some for loops.Owen Anderson2014-03-071-8/+4
| | | | llvm-svn: 203306
* Remove unused method declarationEli Bendersky2014-03-071-1/+0
| | | | llvm-svn: 203301
* R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCCTom Stellard2014-03-072-8/+10
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 203281
* R600/SI: Custom lower i1 storesTom Stellard2014-03-071-0/+6
| | | | | | | | These are sometimes created by the shrink to boolean optimization in the globalopt pass. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 203280
* Don't avoid cfi instructions on the bg/p.Rafael Espindola2014-03-072-6/+0
| | | | | | | The integrated assembler now works for ppc. Since this was the last use of the bg/p predicate and Hal says that it is now dead, drop the predicate too. llvm-svn: 203269
* Remove dead 'break' (dominated by 'return').Ted Kremenek2014-03-071-1/+0
| | | | llvm-svn: 203267
* Remove dead 'return'.Ted Kremenek2014-03-071-1/+0
| | | | llvm-svn: 203265
* "Mac OS/X" -> "Mac OS X" spelling fixes for llvm.Nico Weber2014-03-071-1/+1
| | | | | | Patch from Sean McBride <sean@rogue-research.com>! llvm-svn: 203258
* ARM: Make .unreq directives case-insensitiveDuncan P. N. Exon Smith2014-03-071-1/+1
| | | | | | | | Be case-insensitive when processing .unreq directives. Patch by Lin Zuojian! llvm-svn: 203251
* [SystemZ] Move sign_extend optimization to PerformDAGCombineRichard Sandiford2014-03-072-36/+37
| | | | | | | | | | The target was marking SIGN_EXTEND as Custom because it wanted to optimize certain sign-extended shifts. In all other respects the extension is Legal, so it'd be better to do the optimization in PerformDAGCombine instead. No functional change intended. llvm-svn: 203234
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