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* Constify AArch64CollectLOH.cpp. NFCPete Cooper2015-03-111-7/+7
| | | | llvm-svn: 231969
* [mips][microMIPS] Make usage of NOT16 by code generatorJozef Kolek2015-03-112-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D7748 llvm-svn: 231963
* ARM: simplify and extend byval handlingTim Northover2015-03-115-240/+110
| | | | | | | | | | | | | | | | | | | The main issue being fixed here is that APCS targets handling a "byval align N" parameter with N > 4 were miscounting what objects were where on the stack, leading to FrameLowering setting the frame pointer incorrectly and clobbering the stack. But byval handling had grown over many years, and had multiple layers of cruft trying to compensate for each other and calculate padding correctly. This only really needs to be done once, in the HandleByVal function. Elsewhere should just do what it's told by that call. I also stripped out unnecessary APCS/AAPCS distinctions (now that Clang emits byvals with the correct C ABI alignment), which simplified HandleByVal. rdar://20095672 llvm-svn: 231959
* Remove the need to cache the subtarget in the R600 TargetRegisterInfoEric Christopher2015-03-1112-66/+64
| | | | | | classes. llvm-svn: 231954
* Have getRegPressureSetLimit take a MachineFunction so that aEric Christopher2015-03-112-2/+4
| | | | | | we can inspect the subtarget and function when computing values. llvm-svn: 231951
* Updated with list of possible improvements we are tracking internallyKit Barton2015-03-112-0/+40
| | | | llvm-svn: 231946
* Add the "vbroadcasti128" instruction back.Juergen Ributzka2015-03-111-0/+5
| | | | | | | | | | This is a follow-up to r231182. This adds the "vbroadcasti128" instruction back, but without the intrinsic mapping. Also add a test to check the instriction encoding. This is related to rdar://problem/18742778. llvm-svn: 231945
* Make NaCl's use of .init_array for static constructors match LinuxDerek Schuff2015-03-113-6/+7
| | | | | | | | | | | | Summary: The generic ELF TargetObjectFile defaults to .ctors, but Linux's defaults to .init_array by calling InitializeELF with the value of UseInitArray from TargetMachine. Make NaCl's behavior match. Reviewers: jvoung Differential Revision: http://reviews.llvm.org/D8240 llvm-svn: 231934
* AVX-512: Added SKX forms of shift instructions.Elena Demikhovsky2015-03-112-39/+142
| | | | | | | Added rotation instructions, encoding only. Added encoding tests for all these forms. llvm-svn: 231916
* Have TargetRegisterInfo::getLargestLegalSuperClass take aEric Christopher2015-03-108-18/+24
| | | | | | | MachineFunction argument so that it can look up the subtarget rather than using a cached one in some Targets. llvm-svn: 231888
* Remove subtarget dependence from HexagonRegisterInfo.Eric Christopher2015-03-103-14/+7
| | | | llvm-svn: 231887
* Remove dead code.Eric Christopher2015-03-102-25/+0
| | | | llvm-svn: 231883
* Remove the use of the subtarget in MCCodeEmitter creation andEric Christopher2015-03-1022-53/+19
| | | | | | | update all ports accordingly. Required a couple of small rewrites in handling subtarget features during creation in PPC. llvm-svn: 231861
* Create symbols marking the start of a section earlier.Rafael Espindola2015-03-101-1/+1
| | | | | | | | | This lets us pass the symbol to the constructor and avoid the mutable field. This also opens the way for outputting the symbol only when needed, instead of outputting them at the start of the file. llvm-svn: 231859
* Remove createAMDGPUMCCodeEmitter and instead just register the correctEric Christopher2015-03-103-16/+7
| | | | | | | MCCodeEmitter creation routine based on TargetMachine since the only 64-bit R600 gpus are part of the GCN target. llvm-svn: 231856
* [Hexagon] Adding frame index + add load/store patterns.Colin LeMahieu2015-03-102-5/+20
| | | | llvm-svn: 231850
* [Hexagon] Simplifying deallocret definitions.Colin LeMahieu2015-03-101-12/+3
| | | | llvm-svn: 231847
* [Hexagon] Separating InstHexagon from OpcodeHexagon.Colin LeMahieu2015-03-103-47/+57
| | | | llvm-svn: 231844
* Add support for part-word atomics for PPCNemanja Ivanovic2015-03-107-67/+141
| | | | | | http://reviews.llvm.org/D8090#inline-67337 llvm-svn: 231843
* [AArch64] Avoid going through GPRs for across-vector instructions.Ahmed Bougacha2015-03-103-119/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds new node types for each intrinsic. For instance, for addv, we have AArch64ISD::UADDV, such that: (v4i32 (uaddv ...)) is the same as (v4i32 (scalar_to_vector (i32 (int_aarch64_neon_uaddv ...)))) that is, (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (i32 (int_aarch64_neon_uaddv ...)), ssub) In a combine, we transform all such across-vector-lanes intrinsics to: (i32 (extract_vector_elt (uaddv ...), 0)) This has one big advantage: by making the extract_element explicit, we enable the existing patterns for lane-aware instructions to fire. This lets us avoid needlessly going through the GPRs. Consider: uint32x4_t test_mul(uint32x4_t a, uint32x4_t b) { return vmulq_n_u32(a, vaddvq_u32(b)); } We now generate: addv.4s s1, v1 mul.4s v0, v0, v1[0] instead of the previous: addv.4s s1, v1 fmov w8, s1 dup.4s v1, w8 mul.4s v0, v1, v0 rdar://20044838 llvm-svn: 231840
* [AArch64] Remove integer INSvi*lane patterns. NFCI.Ahmed Bougacha2015-03-101-4/+0
| | | | | | | | | | | | | | | | | | | | | | | Most are redundant, and they never seem to fire. The V128 integer patterns already exist in the INS multiclass. The duplicates only fire when the vector index type isn't i64, because they accept "imm" instead of an explicit "i64", as the instruction definition patterns do. TLI::getVectorIdxTy is i64 on AArch64, so this should never happen. Also, one of them had a typo: for i64, INSvi32lane was used. I noticed because I mistakenly used an explicit i32 as the idx type, and got ins.s for an i64 vector_insert. The V64 patterns also don't seem to ever fire, as V64 vector extract/insert are legalized to V128. The equivalent float patterns are unique and useful, so keep them. No functional change intended; none exhibited on the LIT and LNT tests. llvm-svn: 231838
* Don't use LLVM_LIBRARY_VISIBILITY in cpp files.Benjamin Kramer2015-03-101-1/+3
| | | | llvm-svn: 231831
* [Hexagon] Adding nodes for PIC support.Colin LeMahieu2015-03-102-9/+55
| | | | llvm-svn: 231829
* [Hexagon] Adding DuplexInst instruction format and duplex class defs.Colin LeMahieu2015-03-103-3/+116
| | | | llvm-svn: 231828
* Change the generation of the vmuluwm instruction to be based on the MUL opcode.Kit Barton2015-03-102-3/+9
| | | | | | Phabricator review: http://reviews.llvm.org/D8185 llvm-svn: 231827
* [Hexagon] Adding nodes for vector insert/extract lowering.Colin LeMahieu2015-03-102-0/+76
| | | | llvm-svn: 231825
* [Hexagon] Renaming HexagonJT to JT and adding CP for constantpool.Colin LeMahieu2015-03-103-6/+9
| | | | llvm-svn: 231824
* NVPTX: move NVPTXAllocaHoisting into the cpp fileBenjamin Kramer2015-03-103-34/+35
| | | | | | Also initialize without using static initialization. llvm-svn: 231822
* NVPTX: Remove copy of LLVMInitializeNVPTXAsmPrinter.Benjamin Kramer2015-03-101-7/+0
| | | | | | | | If anyone is using this for some strange reason, LLVMInitializeNVPTXAsmPrinter does exactly the same thing and is what other LLVM tools are calling. llvm-svn: 231810
* Hexagon: Remove unused InstrMapping.Benjamin Kramer2015-03-101-8/+0
| | | | llvm-svn: 231809
* R600/SI: Add _IDXEN and _BOTHEN variants for buffer_storeTom Stellard2015-03-101-0/+15
| | | | llvm-svn: 231798
* R600/SI: Re-order MUBUF operands to match asm strings.Tom Stellard2015-03-103-20/+19
| | | | llvm-svn: 231797
* R600/SI: Move kill flag to second instruction when splitting SMRDTom Stellard2015-03-101-5/+12
| | | | | | | This fixes a machine verifier error in the salu-to-valu.ll, which would have been exposed by a future commit. llvm-svn: 231796
* R600/SI: Add 32-bit encoding of v_cndmask_b32Tom Stellard2015-03-103-6/+25
| | | | | | | This was done by refactoring the v_cndmask_b32 tablegen definition to use inherit from VOP2Inst. llvm-svn: 231795
* Hexagon: Remove pass that does nothing at allBenjamin Kramer2015-03-104-106/+0
| | | | llvm-svn: 231791
* Removing dead code to silence warning C4060: switch statement contains no ↵Aaron Ballman2015-03-101-14/+0
| | | | | | 'case' or 'default' labels; NFC. llvm-svn: 231785
* Remove incredibly confusing isBaseAddressKnownZero.Rafael Espindola2015-03-101-1/+0
| | | | | | | | | | | | | | | When referring to a symbol in a dwarf section on ELF we should use .long foo instead of .long foo - .debug_something because ELF is unaware of the content of the sections and therefore needs relocations. This has nothing to do with optimizing a -0. llvm-svn: 231751
* Use a better name for compile unit labels.Rafael Espindola2015-03-101-1/+0
| | | | | | | | | | | | | They mark the start of a compile unit, so name them .Lcu_*. Using Section->getLabelBeginName() makes it looks like they mark the start of the section. While at it, switch to createTempSymbol to avoid collisions with labels created in inline assembly. Not sure if a "don't crash" test is worth it. With this getLabelBeginName is dead, delete it. llvm-svn: 231750
* DataLayout is mandatory, update the API to reflect it with references.Mehdi Amini2015-03-107-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Now that the DataLayout is a mandatory part of the module, let's start cleaning the codebase. This patch is a first attempt at doing that. This patch is not exactly NFC as for instance some places were passing a nullptr instead of the DataLayout, possibly just because there was a default value on the DataLayout argument to many functions in the API. Even though it is not purely NFC, there is no change in the validation. I turned as many pointer to DataLayout to references, this helped figuring out all the places where a nullptr could come up. I had initially a local version of this patch broken into over 30 independant, commits but some later commit were cleaning the API and touching part of the code modified in the previous commits, so it seemed cleaner without the intermediate state. Test Plan: Reviewers: echristo Subscribers: llvm-commits From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 231740
* Remove an unused variable.Eric Christopher2015-03-101-1/+0
| | | | llvm-svn: 231730
* [Hexagon] Removing unused patterns.Colin LeMahieu2015-03-091-61/+0
| | | | llvm-svn: 231723
* [Hexagon] Use single tailcall pseudoinst and fix checking for label jumping ↵Colin LeMahieu2015-03-094-15/+42
| | | | | | versus tail calling. llvm-svn: 231713
* [Hexagon] Reapply r231699. Remove assumption that second operand is an ↵Colin LeMahieu2015-03-094-144/+20
| | | | | | immediate when checking if A2_tfrsi is combinable. llvm-svn: 231710
* [Hexagon] Reverting r231699Colin LeMahieu2015-03-092-5/+138
| | | | llvm-svn: 231703
* [Hexagon] Updating constant set to simpler versions.Colin LeMahieu2015-03-092-138/+5
| | | | llvm-svn: 231699
* TableGen: Use 'enum : uint64_t' for feature flags to fix -WmicrosoftReid Kleckner2015-03-094-0/+7
| | | | | | | | | | | | | clang-cl would warn that this value is not representable in 'int': enum { FeatureX = 1ULL << 31 }; All MS enums are 'ints' unless otherwise specified, so we have to use an explicit type. The AMDGPU target just hit 32 features, triggering this warning. Now that we have C++11 strong enum types, we can also eliminate the 'const uint64_t' codepath from tablegen and just use 'enum : uint64_t'. llvm-svn: 231697
* Remove the remaining uses of abs64 and nuke it.Benjamin Kramer2015-03-093-5/+5
| | | | | | std::abs works just fine and we're already using it in many places. NFC intended. llvm-svn: 231696
* [Hexagon] Removing old halfword codegen instructions and updating const32/64 ↵Colin LeMahieu2015-03-093-67/+62
| | | | | | splitting. llvm-svn: 231695
* [Hexagon] Eliminating immediate condition set.Colin LeMahieu2015-03-095-189/+4
| | | | llvm-svn: 231693
* [Hexagon] Removing TFR_condset_ir/TFR_condset_ri modeling.Colin LeMahieu2015-03-094-64/+0
| | | | llvm-svn: 231689
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