summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* [MachineCombiner] Support for floating-point FMA on ARM64 (re-commit r267098)Gerolf Hoflehner2016-04-244-35/+557
| | | | | | | | | | | | | | | | | | | The original patch caused crashes because it could derefence a null pointer for SelectionDAGTargetInfo for targets that do not define it. Evaluates fmul+fadd -> fmadd combines and similar code sequences in the machine combiner. It adds support for float and double similar to the existing integer implementation. The key features are: - DAGCombiner checks whether it should combine greedily or let the machine combiner do the evaluation. This is only supported on ARM64. - It gives preference to throughput over latency: the heuristic used is to combine always in loops. The targets decides whether the machine combiner should optimize for throughput or latency. - Supports for fmadd, f(n)msub, fmla, fmls patterns - On by default at O3 ffast-math llvm-svn: 267328
* [X86] Remove isel patterns for selecting tzcnt/lzcnt from ↵Craig Topper2016-04-241-80/+0
| | | | | | cmove/ne+cttz/ctlz. These are folded by DAG combine now. llvm-svn: 267326
* Fix an assertion that can never fire because the condition ANDed with the ↵Craig Topper2016-04-241-1/+1
| | | | | | string is just true or 1. llvm-svn: 267324
* Fix a couple assertions that can never fire because they just contained the ↵Craig Topper2016-04-242-2/+2
| | | | | | text string which always evaluates to true. Add a ! so they'll evaluate to false. llvm-svn: 267312
* [X86] Fix patterns that turn cmove/cmovne+ctlz/cttz into lzcnt/tzcnt ↵Craig Topper2016-04-241-30/+24
| | | | | | instructions. Only one of the conditions should be valid for each pattern, not both. Update tests accordingly. llvm-svn: 267311
* [MC/ELF] Implement support for GOTPCRELX/REX_GOTPCRELX.Davide Italiano2016-04-242-5/+25
| | | | | | | | | The option to control the emission of the new relocations is -relax-relocations (blatantly copied from GNU as). It can't be enabled by default because it breaks relatively recent versions of ld.bfd/ld.gold (late 2015). llvm-svn: 267307
* [MC/ELF] Pass Fixup to getRelocType64.Davide Italiano2016-04-231-2/+3
| | | | | | In preparation for other changes. llvm-svn: 267300
* Revert "[AArch64] Fix optimizeCondBranch logic."Renato Golin2016-04-231-5/+5
| | | | | | This reverts commit r267206, as it broke self-hosting on AArch64. llvm-svn: 267294
* [Hexagon] Set ctlz_zero_undef/cttz_zero_undef to Expand so LegalizeDAG will ↵Craig Topper2016-04-233-16/+8
| | | | | | convert them to ctlz/cttz. Remove the now unneccessary isel patterns. NFC llvm-svn: 267266
* [NVPTX] Set ctlz_zero_undef to Expand so LegalizeDAG will convert it to ↵Craig Topper2016-04-232-10/+3
| | | | | | ctlz. Remove the now unneccessary isel patterns. NFC llvm-svn: 267265
* [WebAssembly] Set ctlz_zero_undef/cttz_zero_undef to Expand so LegalizeDAG ↵Craig Topper2016-04-232-7/+1
| | | | | | will convert them to ctlz/cttz. Remove the now unneccessary isel patterns. NFC llvm-svn: 267264
* AMDGPU: sext_inreg (srl x, K), vt -> bfe x, K, vt.SizeMatt Arsenault2016-04-221-0/+16
| | | | llvm-svn: 267244
* AMDGPU: Re-visit nodes in performAndCombineMatt Arsenault2016-04-221-0/+5
| | | | | | This fixes test regressions when i64 loads/stores are made promote. llvm-svn: 267240
* Differential Revision: http://reviews.llvm.org/D19040Sriraman Tallam2016-04-222-4/+19
| | | | llvm-svn: 267229
* CodeGen: Use PLT relocations for relative references to unnamed_addr functions.Peter Collingbourne2016-04-223-40/+23
| | | | | | | | | | | | | The relative vtable ABI (PR26723) needs PLT relocations to refer to virtual functions defined in other DSOs. The unnamed_addr attribute means that the function's address is not significant, so we're allowed to substitute it with the address of a PLT entry. Also includes a bonus feature: addends for COFF image-relative references. Differential Revision: http://reviews.llvm.org/D17938 llvm-svn: 267211
* [AArch64] Fix optimizeCondBranch logic.Quentin Colombet2016-04-221-5/+5
| | | | | | | | | | | | | The opcode for the optimized branch does not depend on the size of the activate bits in the AND masks, but the AND opcode itself. Indeed, we need to use a X or W variant based on the AND variant not based on whether the mask fits into the related variant. Otherwise, we may end up using the W variant of the optimized branch for 64-bit register inputs! This fixes the last make check verifier issues for AArch64: PR27479. llvm-svn: 267206
* [AArch64] When creating MRS instruction, make sure the destination register isQuentin Colombet2016-04-221-2/+1
| | | | | | | | declared as a definition. This fixes the machine verifier error for CodeGen/AArch64/nzcv-save.ll. llvm-svn: 267185
* [AArch64][AdvSIMDScalar] Update the kill flags correctly.Quentin Colombet2016-04-221-30/+45
| | | | | | | | | | | | | | | | | | | We used to simply set the kill flags to true when transforming a scalar instruction to a vector one. SrcScalar1 = copy SrcVector1 ... = opScalar SrcScalar1 => SrcScalar1 = copy SrcVector1 ... = opVector SrcVector1<kill> This is obviously wrong. The proper update consists in: 1. Propagate the kill status from the copy to the new opVector 2. Reset the kill status on the copy, since the live-range of SrcVector1 got extended. This fixes some of the machine verifier errors for AArch64 with make check. llvm-svn: 267180
* [Hexagon] Use common Pat classes for selecting code for intrinsicsKrzysztof Parzyszek2016-04-224-332/+361
| | | | llvm-svn: 267178
* [Hexagon] Properly close live range in HexagonBlockRangesKrzysztof Parzyszek2016-04-221-1/+1
| | | | llvm-svn: 267173
* [AMDGPU] Insert nop pass: take care of outstanding feedbackKonstantin Zhuravlyov2016-04-222-21/+18
| | | | | | | | | | | - Switch few loops to range-based for loops - Fix nop insertion at the end of BB - Fix formatting - Check for endpgm Differential Revision: http://reviews.llvm.org/D19380 llvm-svn: 267167
* [mips][microMIPS] Revert commit r266861.Zoran Jovanovic2016-04-2210-170/+8
| | | | | | Commit r266861 was the reason for failing tests in LLVM test suite. llvm-svn: 267166
* [Hexagon] Teach mux expansion how to deal with undef predicatesKrzysztof Parzyszek2016-04-221-5/+13
| | | | llvm-svn: 267165
* [Hexagon] Add definitions for trap/pause instructionsKrzysztof Parzyszek2016-04-221-0/+21
| | | | | | Also add tests for other instructions from HexagonSystemInst.td. llvm-svn: 267162
* Emit code16 in assembly in 16-bit modeNirav Dave2016-04-221-0/+6
| | | | | | | | | | | | | | | Summary: When generating assembly using -m16 we must explicitly mark it as 16-bit. Emit .code16 at beginning of file. Fixes wrong results when using -fno-integrated-as. Reviewers: dwmw2 Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19392 llvm-svn: 267152
* [mips] Fix select patterns for MIPS64Simon Dardis2016-04-221-1/+1
| | | | | | | | | | | | | | When targetting MIPS64R6 some of the patterns for select were guarded by a broken predicate. The predicate was supposed to test if a constant value could fit in a 16 bit zero-extended field. Instead the value was tested to fit in a 16 bit sign-extended field. For negative constants of native word width this resulted in wrong code generation. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D19378 llvm-svn: 267151
* [mips] Fix a small typo that would leave BLTZC out of getAnalyzableBrOpc().'Vasileios Kalintiris2016-04-221-1/+1
| | | | llvm-svn: 267149
* [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructionsHrvoje Varga2016-04-224-3/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D19354 llvm-svn: 267137
* [mips][microMIPS] Add R_MICROMIPS_PC18_S3 relocationZoran Jovanovic2016-04-224-2/+23
| | | | | | Differential Revision: http://reviews.llvm.org/D15026 llvm-svn: 267130
* Revert r267098 - [MachineCombiner] Support for floating-point FMA on ARM64Daniel Sanders2016-04-224-557/+35
| | | | | | It introduced buildbot failures on clang-cmake-mips, clang-ppc64le-linux, among others. llvm-svn: 267127
* [X86]: Changing cost for “TRUNCATE v16i32 to v16i8” in SSE4.1 mode.Ashutosh Nema2016-04-221-2/+0
| | | | | | | | | | | | | | Summary: rL256194 transforms truncations between vectors of integers into PACKUS/PACKSS operations during DAG combine. This generates better code for truncate, so cost of truncate needs to be changed but looks like it got changed only in SSE2 table Whereas this change is also applicable for SSE4.1, so the cost of truncate needs to be changed for that as well. Cost of “TRUNCATE v16i32 to v16i8” & “TRUNCATE v16i16 to v16i8” should be same in SSE4.1 & SSE2 table. Removing their cost from SSE4.1, so it will fall back to SSE2. Reviewers: Simon Pilgrim llvm-svn: 267123
* [Sparc] This provides support for itineraries on Sparc.Chris Dewhurst2016-04-225-159/+417
| | | | | | | | | | | | Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future. The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this. As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary. Phabricator Review: http://reviews.llvm.org/D19359 llvm-svn: 267121
* The following code would not work before this patch, due to the inability to ↵Chris Dewhurst2016-04-221-1/+1
| | | | | | | | | | | | | | | | | | | | | take the address of a global object: void func1() { ... } int main(int argc, char** argv) { void (*pFunc)(); pFunc = &func1 pFunc(); ... } Phabricator review: http://reviews.llvm.org/D19368 llvm-svn: 267120
* [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructionsZlatko Buljan2016-04-223-1/+60
| | | | | | Differential Revision: http://reviews.llvm.org/D18687 llvm-svn: 267114
* Fix some spelling mistakesDavid Majnemer2016-04-221-2/+2
| | | | llvm-svn: 267112
* [SystemZ] Mark CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF as Expand instead of Custom ↵Craig Topper2016-04-221-8/+2
| | | | | | since the custom logic just did what Expand does when CTTZ/CTLZ are Legal. NFC llvm-svn: 267109
* [Lanai] Set CTLZ_ZERO_UNDEF/CTTZ_ZERO_UNDEF to Expand instead of Legal so ↵Craig Topper2016-04-222-11/+2
| | | | | | they will be converted to CTLZ/CTTZ by LegalizeDAG. Remove extra instructions that only existed to to contain patterns that match the zero_undef operations. NFC llvm-svn: 267108
* [Lanai] Remove unused methods declarations. NFCCraig Topper2016-04-221-3/+0
| | | | llvm-svn: 267107
* AMDGPU/SI: add llvm.amdgcn.ps.live intrinsicNicolai Haehnle2016-04-224-16/+55
| | | | | | | | | | | | | | | | | | | | | | | Summary: This intrinsic returns true if the current thread belongs to a live pixel and false if it belongs to a pixel that we are executing only for derivative computation. It will be used by Mesa to implement gl_HelperInvocation. Note that for pixels that are killed during the shader, this implementation also returns true, but it doesn't matter because those pixels are always disabled in the EXEC mask. This unearthed a corner case in the instruction verifier, which complained about a v_cndmask 0, 1, exec, exec<imp-use> instruction. That's stupid but correct code, so make the verifier accept it as such. Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19191 llvm-svn: 267102
* [AVX512] Teach lowering to use vplzcntd/q to implement 128/256-bit ↵Craig Topper2016-04-221-9/+6
| | | | | | CTTZ_ZERO_UNDEF even without VLX support. We can just extend to 512-bits and extract like we do for CTLZ. llvm-svn: 267100
* [MachineCombiner] Support for floating-point FMA on ARM64Gerolf Hoflehner2016-04-224-35/+557
| | | | | | | | | | | | | | | | Evaluates fmul+fadd -> fmadd combines and similar code sequences in the machine combiner. It adds support for float and double similar to the existing integer implementation. The key features are: - DAGCombiner checks whether it should combine greedily or let the machine combiner do the evaluation. This is only supported on ARM64. - It gives preference to throughput over latency: the heuristic used is to combine always in loops. The targets decides whether the machine combiner should optimize for throughput or latency. - Supports for fmadd, f(n)msub, fmla, fmls patterns - On by default at O3 ffast-math llvm-svn: 267098
* [WebAssembly] Limit alignment hints to natural alignment.Dan Gohman2016-04-211-3/+9
| | | | | | This follows the current binary format rules. llvm-svn: 267082
* ARM: restrict register class for WIN__DBZCHKSaleem Abdulrasool2016-04-211-2/+2
| | | | | | | | | | | WIN__DBZCHK will insert a CBZ instruction into the stream. This instruction reserves 3 bits for the condition register (rn). As such, we must ensure that we restrict the register to a low register. Use the tGPR class instead of GPR to ensure that this is properly constrained. In debug builds, we would attempt to use lr as a condition register which would silently get truncated with no hint that the register selection was incorrect. llvm-svn: 267080
* MachO: enable .data_region directives everywhereTim Northover2016-04-211-1/+0
| | | | | | | | | | We'd disabled them on x86 because back in the early days some host tools couldn't handle the new load commands. This no longer holds: anyone capable of deploying Clang should be able to deploy its copies of ar/ranlib/etc. rdar://25254790 llvm-svn: 267075
* [Hexagon] Properly recognize register alt namesKrzysztof Parzyszek2016-04-213-38/+47
| | | | llvm-svn: 267038
* [Hexagon] Expand handling of the small-data/bss sectionKrzysztof Parzyszek2016-04-214-67/+367
| | | | llvm-svn: 267034
* [RegisterBankInfo] Change the API for the verify methods.Quentin Colombet2016-04-211-1/+1
| | | | | | | Return bool instead of void so that it is natural to put the calls into asserts. llvm-svn: 267033
* AMDGPU: Fix debug name of pass to better matchMatt Arsenault2016-04-211-1/+1
| | | | | | I get this wrong every time I try to debug this. llvm-svn: 267030
* Split IntrReadArgMem into IntrReadMem and IntrArgMemOnlyNicolai Haehnle2016-04-211-1/+1
| | | | | | | | | | | | | | | | | | Summary: IntrReadWriteArgMem simply becomes IntrArgMemOnly. So there are fewer intrinsic properties that express their orthogonality better, and correspond more closely to the corresponding IR attributes. Suggested by: Philip Reames Reviewers: joker.eph, reames, tstellarAMD Subscribers: jholewinski, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19291 llvm-svn: 267021
* [PowerPC] [SSP] Fix stack guard load for 32-bit.Marcin Koscielnicki2016-04-211-1/+1
| | | | | | | | r266809 incorrectly used LD to load the stack guard, it should be LWZ. Differential Revision: http://reviews.llvm.org/D19358 llvm-svn: 267017
OpenPOWER on IntegriCloud