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* Actually remove the Mangler from the AsmPrinter and clean up the places it ↵Eric Christopher2016-09-167-15/+7
| | | | | | was "used" but not used. llvm-svn: 281749
* Fix a hidden use of grabbing the Mangler from the AsmPrinter and updateEric Christopher2016-09-161-4/+4
| | | | | | accordingly. llvm-svn: 281748
* [AArch64][GlobalISel] Add default regbank mapping for int<>FP.Ahmed Bougacha2016-09-161-0/+10
| | | | llvm-svn: 281739
* [AArch64][GlobalISel] Add default regbank mapping for G_FCMP.Ahmed Bougacha2016-09-161-0/+10
| | | | llvm-svn: 281738
* [AArch64][GlobalISel] Add default regbank mapping for FP ops.Ahmed Bougacha2016-09-161-1/+18
| | | | | | These should have all their operands - even scalars - go on FPR. llvm-svn: 281737
* [AArch64][GlobalISel] Add default regbank mappings for mixed-type ops.Ahmed Bougacha2016-09-161-18/+36
| | | | | | | | We used to only support instructions with same-type operands. Instead, use the per-register type information to map each operand more accurately. llvm-svn: 281734
* [mips] Fix previous revert r281726.Simon Dardis2016-09-161-36/+0
| | | | llvm-svn: 281729
* Place the lowered phi instruction(s) before the DEBUG_VALUE entryKeith Walker2016-09-161-1/+1
| | | | | | | | | | | | | | | | When a phi node is finally lowered to a machine instruction it is important that the lowered "load" instruction is placed before the associated DEBUG_VALUE entry describing the value loaded. Renamed the existing SkipPHIsAndLabels to SkipPHIsLabelsAndDebug to more fully describe that it also skips debug entries. Then used the "new" function SkipPHIsAndLabels when the debug information should not be skipped when placing the lowered "load" instructions so that it is placed before the debug entries. Differential Revision: https://reviews.llvm.org/D23760 llvm-svn: 281727
* Revert "[mips] Fix aui/daui/dahi/dati for MIPSR6"Simon Dardis2016-09-167-39/+47
| | | | | | This reverts r281724. Still need dsanders to accept this. llvm-svn: 281726
* [mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis2016-09-167-11/+75
| | | | | | | | | | | | For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
* Reverting r281719, this is causing buildbot failures and timeouts again.Sjoerd Meijer2016-09-161-18/+1
| | | | llvm-svn: 281722
* [AArch64][GlobalISel] Use the generic DefaultMapping as the default.Ahmed Bougacha2016-09-161-2/+1
| | | | | | | This lets generic logic handle the common case, instead of having to implement applyMappingImpl for each instruction. llvm-svn: 281720
* This is an attempt to reapply r280808: [ARM] Lower UDIV+UREM to UDIV+MLSSjoerd Meijer2016-09-161-1/+18
| | | | | | | | | | (and the same for SREM) This was causing buildbot failures earlier (time outs in the LNT suite). However, we haven't been able to reproduce this and are suspecting this was caused by another (reverted) patch. llvm-svn: 281719
* Trying to fix Mangler memory leak in TargetLoweringObjectFile.Eric Liu2016-09-161-0/+2
| | | | | | | | | | | | | | Summary: `TargetLoweringObjectFile` can be re-used and thus `TargetLoweringObjectFile::Initialize()` can be called multiple times causing `Mang` pointer memory leak. Reviewers: echristo Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D24659 llvm-svn: 281718
* [ARM] Promote small global constants to constant poolsJames Molloy2016-09-165-3/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a constant is unamed_addr and is only used within one function, we can save on the code size and runtime cost of an indirection by changing the global's storage to inside the constant pool. For example, instead of: ldr r0, .CPI0 bl printf bx lr .CPI0: &format_string format_string: .asciz "hello, world!\n" We can emit: adr r0, .CPI0 bl printf bx lr .CPI0: .asciz "hello, world!\n" This can cause significant code size savings when many small strings are used in one function (4 bytes per string). This recommit contains fixes for a nasty bug related to fast-isel fallback - because fast-isel doesn't know about this optimization, if it runs and emits references to a string that we inline (because fast-isel fell back to SDAG) we will end up with an inlined string and also an out-of-line string, and we won't emit the out-of-line string, causing backend failures. It also contains fixes for emitting .text relocations which made the sanitizer bots unhappy. llvm-svn: 281715
* Move the Mangler from the AsmPrinter down to TLOF and clean up theEric Christopher2016-09-1627-136/+97
| | | | | | TLOF API accordingly. llvm-svn: 281708
* Remove unused function getMang().Eric Christopher2016-09-161-3/+0
| | | | llvm-svn: 281707
* [AArch64] Support for FP FMA when -ffp-contract=fastEvandro Menezes2016-09-151-3/+5
| | | | | | | | | | | | Currently, the machine combiner can proceed matching when -ffast-math is on. It should also match when only -ffp-contract=fast is specified as was the case before when DAGCombiner was doing the job. Patch by: Abderrazek Zaafrani <a.zaafrani@samsung.com>. Differential Revision: https://reviews.llvm.org/D24366 llvm-svn: 281649
* Revert "[ARM] Promote small global constants to constant pools"Evgeniy Stepanov2016-09-154-155/+1
| | | | | | This reverts r281604, which adds text relocations to ARM binaries. llvm-svn: 281645
* [mips][ias] Enable IAS by default for N64 on Debian mips64el.Simon Dardis2016-09-151-0/+4
| | | | | | | | | | | | | | | | | | | Unfortunately we can't enable it for all N64 because it is not yet possible to distinguish N32 from N64. N64 has been confirmed to produce identical (within reason) objects to GAS during stage 2 of compiler recursion on N64-abit Fedora. Unfortunately, Fedora's triples do not distinguish N32 from N64 so I can't enable it by default there. I'm currently repeating this testing for Debian mips64el but it's very unlikely to produce a different result. Patch by: Daniel Sanders Reviewers: sdardis Differential Review: https://reviews.llvm.org/D22678 llvm-svn: 281607
* [ARM] Promote small global constants to constant poolsJames Molloy2016-09-154-1/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a constant is unamed_addr and is only used within one function, we can save on the code size and runtime cost of an indirection by changing the global's storage to inside the constant pool. For example, instead of: ldr r0, .CPI0 bl printf bx lr .CPI0: &format_string format_string: .asciz "hello, world!\n" We can emit: adr r0, .CPI0 bl printf bx lr .CPI0: .asciz "hello, world!\n" This can cause significant code size savings when many small strings are used in one function (4 bytes per string). This recommit contains fixes for a nasty bug related to fast-isel fallback - because fast-isel doesn't know about this optimization, if it runs and emits references to a string that we inline (because fast-isel fell back to SDAG) we will end up with an inlined string and also an out-of-line string, and we won't emit the out-of-line string, causing backend failures. llvm-svn: 281604
* GlobalISel: legalize GEP instructions with small offsets.Tim Northover2016-09-151-0/+6
| | | | llvm-svn: 281602
* GlobalISel: relax type constraints on G_ICMP to allow pointers.Tim Northover2016-09-151-0/+1
| | | | llvm-svn: 281600
* GlobalISel: remove "unsized" LLTTim Northover2016-09-153-7/+5
| | | | | | | | It was only really there as a sentinel when instructions had to have precisely one type. Now that registers are typed, each register really has to have a type that is sized. llvm-svn: 281599
* GlobalISel: cache pointer sizes in LLTTim Northover2016-09-152-5/+5
| | | | | | | Otherwise everything that needs to work out what size they are has to keep a DataLayout handy, which is a bit silly and very annoying. llvm-svn: 281597
* Finish renaming remaining analyzeBranch functionsMatt Arsenault2016-09-1438-82/+80
| | | | llvm-svn: 281535
* Revert "[ARM] Promote small global constants to constant pools"Evgeniy Stepanov2016-09-144-145/+1
| | | | | | | | Breaks Android tests by introducing text relocations to ARM binaries. http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/25362/steps/run%20asan%20lit%20tests%20%5Barm%2Fbullhead-userdebug%2FMTC20F%5D/logs/stdio llvm-svn: 281526
* Revert "AMDGPU: Use SOPK compare instructions"Matt Arsenault2016-09-146-135/+51
| | | | | | Accidentally committed llvm-svn: 281514
* AMDGPU: Use SOPK compare instructionsMatt Arsenault2016-09-146-51/+135
| | | | llvm-svn: 281513
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-1436-60/+60
| | | | | | | analyzeBranch was renamed to use lowercase first, rename the related set to match. llvm-svn: 281506
* AArch64: Use TTI branch functions in branch relaxationMatt Arsenault2016-09-1435-240/+268
| | | | | | | | | The main change is to return the code size from InsertBranch/RemoveBranch. Patch mostly by Tim Northover llvm-svn: 281505
* [x86] fix formatting; NFCSanjay Patel2016-09-141-28/+20
| | | | llvm-svn: 281504
* [X86][SSE] Improve recognition of i64 sitofp conversions that can be ↵Simon Pilgrim2016-09-141-0/+17
| | | | | | | | | | | | performed as i32 (PR29078) Until AVX512DQ we only support i64/vXi64 sitofp conversion as scalars. This patch sees if the sign bit extends far enough that we can truncate to a i32 type and then perform sitofp without loss of precision. Differential Revision: https://reviews.llvm.org/D24345 llvm-svn: 281502
* [X86][SSE] Don't use PSHUFD directly - lower with generic shuffleSimon Pilgrim2016-09-141-17/+1
| | | | | | Remove the last user of the old getTargetShuffleNode helpers llvm-svn: 281499
* getValueType().getScalarSizeInBits() -> getScalarValueSizeInBits(), round 2 ↵Sanjay Patel2016-09-141-3/+2
| | | | | | ; NFCI llvm-svn: 281498
* getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel2016-09-1412-68/+68
| | | | llvm-svn: 281495
* getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCISanjay Patel2016-09-1412-58/+51
| | | | llvm-svn: 281493
* AMDGPU: Support folding FrameIndex operandsMatt Arsenault2016-09-141-9/+26
| | | | | | This avoids test regressions in a future commit. llvm-svn: 281491
* getValueType().getScalarSizeInBits() -> getScalarValueSizeInBits() ; NFCISanjay Patel2016-09-144-11/+9
| | | | llvm-svn: 281490
* getScalarType().getSizeInBits() -> getScalarSizeInBits() ; NFCISanjay Patel2016-09-146-7/+7
| | | | llvm-svn: 281489
* AMDGPU: Improve splitting 64-bit bit ops by constantsMatt Arsenault2016-09-146-88/+272
| | | | | | | | This addresses a TODO to handle operations besides and. This also starts eliminating no-op operations with a constant that can emerge later. llvm-svn: 281488
* [ARM] Promote small global constants to constant poolsJames Molloy2016-09-144-1/+145
| | | | | | | | | | | | | | | | | | | | | | | | If a constant is unamed_addr and is only used within one function, we can save on the code size and runtime cost of an indirection by changing the global's storage to inside the constant pool. For example, instead of: ldr r0, .CPI0 bl printf bx lr .CPI0: &format_string format_string: .asciz "hello, world!\n" We can emit: adr r0, .CPI0 bl printf bx lr .CPI0: .asciz "hello, world!\n" This can cause significant code size savings when many small strings are used in one function (4 bytes per string). llvm-svn: 281484
* [X86][SSE] Removed unused getTargetShuffleNode functionSimon Pilgrim2016-09-141-17/+0
| | | | llvm-svn: 281481
* Fix code-gen crash on Power9 for insert_vector_elt with variable index (PR30189)Nemanja Ivanovic2016-09-142-2/+16
| | | | | | | | | | | This patch corresponds to review: https://reviews.llvm.org/D24021 In the initial implementation of this instruction, I forgot to account for variable indices. This patch fixes PR30189 and should probably be merged into 3.9.1 (I'll open a bug according to the new instructions). llvm-svn: 281479
* Adding missing directive for Power9.Nemanja Ivanovic2016-09-141-1/+1
| | | | | | | | There is currently no codegen for Power9 that depends on the directive so this is NFC for now but will be important in the future. This was missed in r268950 so I'm adding it now. llvm-svn: 281473
* [X86][SSE] Don't blend vector shifts with MOVSS/MOVSD directly, lower from ↵Simon Pilgrim2016-09-141-10/+10
| | | | | | | | generic shuffle Shuffle lowering will correctly lower to MOVSS/MOVSD/PBLEND, improving commutation opportunities llvm-svn: 281471
* Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"James Molloy2016-09-142-138/+5
| | | | | | This reverts commit r281323. It caused chromium test failures and a selfhost failure. llvm-svn: 281451
* GlobalISel: mark pointer stores as legal on AArch64.Tim Northover2016-09-141-1/+1
| | | | llvm-svn: 281448
* This reapplies r281304. The issue was that I had missedSjoerd Meijer2016-09-145-49/+52
| | | | | | to copy the new isAdd field in the tablegen data structure. llvm-svn: 281447
* AVX-512: Fixed a bug in kortest.z intrinsicElena Demikhovsky2016-09-141-1/+1
| | | | | | Lowering was wrong - X86ISD::SETCC node should return i8 type. llvm-svn: 281446
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