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* [mips][sched] Split IIBranch into specific instruction classes.Daniel Sanders2015-09-229-38/+83
| | | | | | | | | | | | | | | | | | | | | Summary: Almost no functional change since the InstrItinData's have been duplicated. The one functional change is to remove IIBranch from the MSA branches. The classes will be assigned to the MSA instructions as part of implementing the P5600 scheduler. II_IndirectBranchPseudo and II_ReturnPseudo can probably be removed. I've preserved the itinerary information for the corresponding pseudo instructions to avoid making a functional change to these pseudos in this patch. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12189 llvm-svn: 248273
* [mips][sched] Temporarily rename IIAlu to IIM16Alu. NFC.Daniel Sanders2015-09-222-61/+62
| | | | | | | | | | | | | | | Summary: The only instructions left in IIAlu are MIPS16 specific. We're not implementing a MIPS16 scheduler at this time so rename the class to make it obvious that they are MIPS16 instructions. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12188 llvm-svn: 248267
* Don't raise inexact when lowering ceil, floor, round, trunc.Stephen Canon2015-09-223-211/+51
| | | | | | | | The C standard has historically not specified whether or not these functions should raise the inexact flag. Traditionally on Darwin, these functions *did* raise inexact, and the llvm lowerings followed that conventions. n1778 (C bindings for IEEE-754 (2008)) clarifies that these functions should not set inexact. This patch brings the lowerings for arm64 and x86 in line with the newly specified behavior. This also lets us fold some logic into TD patterns, which is nice. Differential Revision: http://reviews.llvm.org/D12969 llvm-svn: 248266
* Prune trailing whitespaces.NAKAMURA Takumi2015-09-224-18/+18
| | | | llvm-svn: 248265
* Untabify.NAKAMURA Takumi2015-09-2224-100/+94
| | | | llvm-svn: 248264
* Reformat blank lines.NAKAMURA Takumi2015-09-2213-53/+29
| | | | llvm-svn: 248263
* Reformat comment lines.NAKAMURA Takumi2015-09-227-35/+40
| | | | llvm-svn: 248262
* Reformat.NAKAMURA Takumi2015-09-229-166/+145
| | | | llvm-svn: 248261
* ARMInstrInfo.cpp: Reformat.NAKAMURA Takumi2015-09-221-66/+65
| | | | llvm-svn: 248260
* Fix utf8 chars.NAKAMURA Takumi2015-09-221-1/+1
| | | | llvm-svn: 248259
* [mips][ias] Implement .cpreturn directive.Daniel Sanders2015-09-223-0/+54
| | | | | | | | | | | | | | | | | Summary: Based on a patch by David Chisnall. I've modified the original patch as follows: * Moved the expansion to the TargetStreamers so that the directive isn't expanded when emitting assembly. * Fixed an operand order bug. * Changed the move instructions from DADDu to OR to match recent changes to GAS. Reviewers: vkalintiris Subscribers: llvm-commits, emaste, seanbruno, theraven Differential Revision: http://reviews.llvm.org/D13017 llvm-svn: 248258
* [mips][sched] Added class for WSBHDaniel Sanders2015-09-223-6/+9
| | | | | | | | | | | | | Summary: No functional change since no InstrItinData is provided. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12190 llvm-svn: 248257
* [X86][SSE] Match zero/any extension shuffles that don't start from the first ↵Simon Pilgrim2015-09-221-26/+108
| | | | | | | | | | | | element This patch generalizes the lowering of shuffles as zero extensions to allow extensions that don't start from the first element. It now recognises extensions starting anywhere in the lower 128-bits or at the start of any higher 128-bit lane. The motivation was to reduce the number of high cost pshufb calls, but it also improves the SSE2 case as well. Differential Revision: http://reviews.llvm.org/D12561 llvm-svn: 248250
* AMDGPU: Remove unnecessary checkMatt Arsenault2015-09-221-4/+0
| | | | | | | If the instruction doesn't have enough operands, it either shouldn't be marked as isCommutable or is malformed. llvm-svn: 248242
* [ARM] Do not scale vext with a factorJeroen Ketema2015-09-211-9/+1
| | | | | | | | | | | | | The vext pseudo-instruction takes the number of elements that need to be extracted, not the number of bytes. Hence, use the number of elements directly instead of scaling them with a factor. Reviewers: Silviu Baranga, James Molloy (not reflected in the differential revision) Differential Revision: http://reviews.llvm.org/D12974 llvm-svn: 248208
* [SystemZ] Fix expansion of ISD::FPOW and ISD::FSINCOSUlrich Weigand2015-09-211-0/+2
| | | | | | | | | | | | | The ISD::FPOW and ISD::FSINCOS opcodes default to Legal, but there is no legal instruction for those on SystemZ. This could cause LLVM internal errors. Fixed by setting the operation action to Expand for those opcodes. Also added test cases for all other LLVM IR intrinsics that should generate a library call. (Those already work correctly since the default operation action is fine.) llvm-svn: 248180
* Revert "[ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def"James Molloy2015-09-211-2/+2
| | | | | | | | This was committed without the code review (http://reviews.llvm.org/D12937) being approved. This reverts commit r248152. llvm-svn: 248174
* AMDGPU: Move copy handling under switch like other instructionsMatt Arsenault2015-09-211-5/+10
| | | | llvm-svn: 248172
* [Machine Combiner] Refactor machine reassociation code to be target-independent.Chad Rosier2015-09-216-511/+27
| | | | | | | | | | No functional change intended. Patch by Haicheng Wu <haicheng@codeaurora.org>! http://reviews.llvm.org/D12887 PR24522 llvm-svn: 248164
* [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.defArtyom Skrobov2015-09-211-2/+2
| | | | | | | | | | | | | | | | Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with a FIXME: attached. This patch changes the handling of +t2dsp to be in line with other architecture extensions. Following review comments, also updating the description of FeatureDSPThumb2 in ARM.td. Differential Revision: http://reviews.llvm.org/D12937 llvm-svn: 248152
* [X86][AVX512] add masked version for RSQRT14 & RCP14 Scalar FPAsaf Badouh2015-09-214-46/+39
| | | | | | Differential Revision: http://reviews.llvm.org/D12524 llvm-svn: 248147
* [mips] Allow constant expressions in second argument of .cpsetup.Daniel Sanders2015-09-212-8/+11
| | | | | | | | | | | | | | Summary: Also tightened up the test and made a trivial fix to prevent double-newline after emitting .cpsetup directives. Reviewers: vkalintiris Subscribers: seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D12956 llvm-svn: 248143
* Use makeArrayRef or None to avoid unnecessarily mentioning the ArrayRef type ↵Craig Topper2015-09-211-1/+1
| | | | | | extra times. NFC llvm-svn: 248140
* Don't pass StringRefs around by const reference. Pass by value instead per ↵Craig Topper2015-09-212-6/+6
| | | | | | coding standards. NFC llvm-svn: 248136
* Cleanup places that passed SMLoc by const reference to pass it by value ↵Craig Topper2015-09-204-7/+4
| | | | | | instead. NFC llvm-svn: 248135
* AVX512: Implemented encoding and intrinsics for vcmpss/sd.Igor Breger2015-09-204-42/+129
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12593 llvm-svn: 248121
* [X86][AVX512] extend support in Scalar conversionAsaf Badouh2015-09-203-127/+231
| | | | | | | | | | add scalar FP to Int conversion with truncation intrinsics add scalar conversion FP32 from/to FP64 intrinsics add rounding mode and SAE mode encoding for these intrinsics Differential Revision: http://reviews.llvm.org/D12665 llvm-svn: 248117
* AVX512: vsqrtss/sd encoding and intrinsics implementation.Igor Breger2015-09-203-93/+63
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12102 llvm-svn: 248116
* [X86][AVX512DQ] Add fpclass instruction Asaf Badouh2015-09-205-2/+119
| | | | | | Differential Revision: http://reviews.llvm.org/D12931 llvm-svn: 248115
* [X86] Fix sitofp and uitofp instruction matching failures with long double ↵Michael Kuperstein2015-09-201-9/+14
| | | | | | | | | | | | and avx512 The operation action for i32 and i64 cannot be set to legal, as long double needs custom lowering. Patch by: mitch.l.bodart@intel.com Differential Revision: http://reviews.llvm.org/D12372 llvm-svn: 248114
* AVX512: Implemented intrinsics for vshuff32x4, vshuff64x2, vshufi64x2, ↵Igor Breger2015-09-201-0/+16
| | | | | | | | | | vshufi32x4 Added tests for intrinsics. Differential Revision: http://reviews.llvm.org/D12525 llvm-svn: 248113
* AVX512: Implement instructions encoding, lowering and intrinsicsIgor Breger2015-09-204-65/+137
| | | | | | | | | vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4 Added tests for encoding, lowering and intrinsics. Differential Revision: http://reviews.llvm.org/D11893 llvm-svn: 248111
* ARM: cleanup formattingSaleem Abdulrasool2015-09-201-2/+2
| | | | | | clang-format a line which was poorly formatted. NFC. llvm-svn: 248110
* [X86][SSE] Vectorize CTTZ + CTTZ_ZERO_UNDEFSimon Pilgrim2015-09-191-4/+57
| | | | | | | | | | Now that we have fast vector CTPOP implementations we can use this to speed up vector CTTZ using the pattern (cttz(x) = ctpop((x & -x) - 1)) Additionally, for AVX512CD that provides lzcnt instructions we can use the pattern (cttz_undef(x) = (width - 1) - ctlz(x & -x)) Differential Revision: http://reviews.llvm.org/D12663 llvm-svn: 248091
* AMDGPU: Remove dead codeMatt Arsenault2015-09-195-18/+2
| | | | | | | getCFGStructurizerRegClass is not used for SI, so move it into R600 specific stuff. llvm-svn: 248087
* NFC: Fix indentation and add braces to clarify nested of else-statement.Bob Wilson2015-09-191-2/+3
| | | | llvm-svn: 248086
* Limit the range of processors supported by ARM fast isel to v6 orEric Christopher2015-09-181-0/+4
| | | | | | | | later as that's all that is tested right now. Fixes PR24858. llvm-svn: 248027
* Make MachineScheduler debug output less confusing.James Y Knight2015-09-181-1/+5
| | | | | | At least...a little bit. llvm-svn: 248020
* Scaling up values in ARMBaseInstrInfo::isProfitableToIfCvt() before they are ↵Cong Hou2015-09-181-10/+17
| | | | | | | | | | scaled by a probability to avoid precision issue. In ARMBaseInstrInfo::isProfitableToIfCvt(), there is a simple cost model in which the number of cycles is scaled by a probability to estimate the cost. However, when the number of cycles is small (which is usually the case), there is a precision issue after the computation. To avoid this issue, this patch scales those cycles by 1024 (chosen to make the multiplication a litter faster) before they are scaled by the probability. Other variables are also scaled up for the final comparison. Differential Revision: http://reviews.llvm.org/D12742 llvm-svn: 248018
* [AArch64] Improved bitfield instruction selection.Geoff Berry2015-09-181-11/+67
| | | | | | | | | | | | | | | | | | Summary: For bitfield insert OR matching, check both operands for larger pattern first before checking for smaller pattern. Add pattern for unsigned bitfield insert-in-zero done with SHL+AND. Resolves PR21631. Reviewers: jmolloy, t.p.northover Subscribers: aemerson, rengolin, llvm-commits, mcrosier Differential Revision: http://reviews.llvm.org/D12908 llvm-svn: 248006
* [mips][microMIPS] Fix an invalid read for lwm32 and reserved reglist values.Daniel Sanders2015-09-181-0/+6
| | | | | | | | | | | | | | | Summary: Some values of 'reglist' are reserved and cause the disassembler to read past the end of the Regs array. Treat lwm32's containing reserved values as invalid instructions. Reviewers: zoran.jovanovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12959 llvm-svn: 247990
* [AArch64] Reorder cases to improve readability. NFC.Chad Rosier2015-09-181-9/+9
| | | | llvm-svn: 247989
* [AArch64] Remove some redundant cases. NFC.Chad Rosier2015-09-181-16/+8
| | | | llvm-svn: 247988
* [bpf] expand indirect branchesAlexei Starovoitov2015-09-171-0/+1
| | | | | | | | BPF instruction set doesn't have indirect branches. Expand them. Reported by John Fastabend. llvm-svn: 247951
* [SPARC] Add mulscc.Joerg Sonnenberger2015-09-171-0/+4
| | | | llvm-svn: 247940
* [WinEH] Make funclet return instrs pseudo instrsReid Kleckner2015-09-179-100/+99
| | | | | | | | | This makes catchret look more like a branch, and less like a weird use of BlockAddress. It also lets us get away from llvm.x86.seh.restoreframe, which relies on the old parentfpoffset label arithmetic. llvm-svn: 247936
* [mips] Add assembler support for the .cprestore directive.Daniel Sanders2015-09-173-13/+159
| | | | | | | | | | | | | | | | | | Summary: This assembler directive is used in O32 PIC to restore the current function's $gp after executing JAL's. The $gp is first stored on the stack at a user-specified offset. It has the following format: ".cprestore 8" (where 8 is the offset). This fixes llvm.org/PR20967. Patch by Toma Tabacu. Reviewers: seanbruno, tomatabacu Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D6267 llvm-svn: 247897
* Typos. NFC.Chad Rosier2015-09-171-5/+5
| | | | llvm-svn: 247884
* [mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructionsZoran Jovanovic2015-09-173-20/+40
| | | | | | Differential Revision: http://reviews.llvm.org/D9658 llvm-svn: 247880
* AVX-512: shufflevector for i1 vectors <2 x i1> .. <64 x i1>Elena Demikhovsky2015-09-172-7/+80
| | | | | | | | | | AVX-512 does not provide an instruction that shuffles mask register. So I do the following way: mask-2-simd , shuffle simd , simd-2-mask Differential Revision: http://reviews.llvm.org/D12727 llvm-svn: 247876
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