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* Fix the name of a variable to match its declaration. Fixes build failure ↵Craig Topper2013-03-141-1/+1
| | | | | | from r177014. llvm-svn: 177015
* Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit ↵Craig Topper2013-03-142-0/+13
| | | | | | set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185. llvm-svn: 177014
* Teach X86 MC instruction lowering that VMOVAPSrr and other VEX-encoded ↵Craig Topper2013-03-141-0/+42
| | | | | | register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior. llvm-svn: 177011
* Fix PR15309Michael Liao2013-03-141-1/+2
| | | | | | - Fix the typo on type checking llvm-svn: 177010
* Reset some of the target options which affect code generation.Bill Wendling2013-03-131-0/+26
| | | | | | | | This doesn't reset all of the target options within the TargetOptions object. This is because some of those are ABI-specific and must be determined if it's okay to change those on the fly. llvm-svn: 176986
* R600: Remove unused Outputs variableVincent Lejeune2013-03-132-2/+0
| | | | llvm-svn: 176967
* Add one more overload to make VS2008's debug mody happy.Benjamin Kramer2013-03-131-0/+3
| | | | | | sigh. llvm-svn: 176946
* [mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is forAkira Hatanaka2013-03-139-878/+1106
| | | | | | | | mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
* ARM cost model: Increase the cost for vector casts that use the stackArnold Schwaighofer2013-03-121-0/+8
| | | | | | | | | | | | | | | | | | | | | | | Increase the cost of v8/v16-i8 to v8/v16-i32 casts and truncates as the backend currently lowers those using stack accesses. This was responsible for a significant degradation on MultiSource/Benchmarks/Trimaran/enc-pc1/enc-pc1 where we vectorize one loop to a vector factor of 16. After this patch we select a vector factor of 4 which will generate reasonable code. unsigned char cle[32]; void test(short c) { unsigned short compte; for (compte = 0; compte <= 31; compte++) { cle[compte] = cle[compte] ^ c; } } radar://13220512 llvm-svn: 176898
* Don't reserve R2 on Darwin/PPCHal Finkel2013-03-121-16/+2
| | | | | | | | | | | Now that only the register-scavenger version of the CR spilling code remains, we no longer need the Darwin R2 hack. Darwin can use R0 as a spare register in any case where the System V ABI uses it (R0 is special architecturally, and so is reserved under all common ABIs). A few test cases needed to be updated to reflect the register-allocation changes. llvm-svn: 176868
* PPC should always use the register scavenger for CR spillingHal Finkel2013-03-123-137/+29
| | | | | | | | This removes the -disable-ppc[32|64]-regscavenger options; the code that uses the register scavenger has been working well (and has been the default) for some time, and we don't need options to enable the old (broken) CR spilling code. llvm-svn: 176865
* [mips] Rename function and variable names to start with proper case. Fix typos.Akira Hatanaka2013-03-123-571/+493
| | | | | | Delete commented-out code. llvm-svn: 176844
* Fixes disassembler crashes on 2013 Haswell RTM instructions.Kevin Enderby2013-03-111-1/+1
| | | | | | rdar://13318048 llvm-svn: 176828
* R600: Fix JUMP handling so that MachineInstr verification can occurVincent Lejeune2013-03-114-45/+59
| | | | | | This allows R600 Target to use the newly created -verify-misched llc flag llvm-svn: 176819
* R600MachineScheduler.cpp: Fix use cases of dbgs(). Don't include <iostream> ↵NAKAMURA Takumi2013-03-111-1/+2
| | | | | | here. llvm-svn: 176797
* Correct this error message, and most importantly make it distinct from theNick Lewycky2013-03-101-1/+1
| | | | | | error above. Based on a patch by Peter Zotov! llvm-svn: 176794
* Cleanup #includes.Jakub Staszak2013-03-101-1/+2
| | | | llvm-svn: 176787
* Don't glue users to extract_subreg when selecting the llvm.arm.ldrexdLang Hames2013-03-091-6/+4
| | | | | | | | | intrinsic - it can cause impossible-to-schedule subgraphs to be introduced. PR15053. llvm-svn: 176777
* TLI: Microoptimize calls to strlen+memcmp to strncmp.Benjamin Kramer2013-03-091-2/+24
| | | | | | | | The strlen+memcmp was hidden in a call to StringRef::operator==. We check if there are any null bytes in the string upfront so we can simplify the comparison Small speedup when compiling code with many function calls. llvm-svn: 176766
* R600: Optimize another selectcc caseTom Stellard2013-03-081-11/+20
| | | | | | | | fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne -> selectcc x, y, a, b, cc Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 176700
* R600: Improve custom lowering of select_ccTom Stellard2013-03-082-37/+42
| | | | | | | | | Two changes: 1. Prefer SET* instructions when possible 2. Handle the CND*_INT case with floating-point args Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 176699
* R600: Change operation action from Custom to Expand for BR_CCTom Stellard2013-03-082-43/+2
| | | | | Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 176698
* R600: Change operation action from Custom to Expand for SETCCTom Stellard2013-03-082-46/+2
| | | | | Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 176697
* R600: Set BooleanContents to ZeroOrNegativeOneBooleanContentTom Stellard2013-03-081-0/+1
| | | | | Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 176696
* DAGCombiner: Use correct value type for checking legality of BR_CC v3Tom Stellard2013-03-086-6/+24
| | | | | | | | | | | | | LegalizeDAG.cpp uses the value of the comparison operands when checking the legality of BR_CC, so DAGCombiner should do the same. v2: - Expand more BR_CC value types for NVPTX v3: - Expand correct BR_CC value types for Hexagon, Mips, and XCore. llvm-svn: 176694
* Hexagon: Add patterns for zero extended loads from i1->i64.Jyotsna Verma2013-03-082-0/+24
| | | | llvm-svn: 176689
* AArch64: expand sincos operations, we don't support them.Tim Northover2013-03-081-0/+3
| | | | | | Patch based on Mans Rullgard's. llvm-svn: 176688
* R600/SI: Use source schedulerMichel Danzer2013-03-081-0/+2
| | | | | | | | | | | | | | | This is certainly not the last word on scheduling for this target, but right now this allows a few apps to run / finish with radeonsi, most notably UT2004 / Lightsmark. They fail to compile some shaders with the default scheduler because it ends up trying to spill registers, which we don't support yet (and which is probably a bad idea in general for performance if it can be avoided). NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176687
* ArrayRefize some code. No functionality change.Benjamin Kramer2013-03-074-36/+26
| | | | llvm-svn: 176648
* Hexagon: Handle i8, i16 and i1 Var Args.Jyotsna Verma2013-03-071-0/+10
| | | | llvm-svn: 176647
* Hexagon: Add support to lower block address.Jyotsna Verma2013-03-074-0/+28
| | | | llvm-svn: 176637
* X86: Fold EXTRACT_SUBVECTORs of a BUILD_VECTOR into a smaller BUILD_VECTOR.Benjamin Kramer2013-03-071-0/+5
| | | | | | | | | | That can usually be lowered efficiently and is common in sandybridge code. It would be nice to do this in DAGCombiner but we can't insert arbitrary BUILD_VECTORs this late. Fixes PR15462. llvm-svn: 176634
* R600/SI: rework input interpolation v2Christian Konig2013-03-0712-321/+46
| | | | | | | | v2: update CMakeLists.txt as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176626
* R600/SI: remove SI_vs_load_buffer_indexChristian Konig2013-03-072-15/+0
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176625
* R600/SI: remove SGPR address space v2Christian Konig2013-03-075-70/+21
| | | | | | | | v2: fix R600 regressions Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176624
* R600/SI: add proper formal parameter handling for SIChristian Konig2013-03-077-22/+163
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176623
* R600/SI: remove shader type intrinsicChristian Konig2013-03-076-18/+18
| | | | | | | | Just encode the type as target specific attribute. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176622
* R600/SI: switch types of SGPRs to v*i8Christian Konig2013-03-074-11/+24
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176621
* R600/SI: fix unused variable warningChristian Konig2013-03-071-1/+0
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176620
* Fix two remaining issue after fixing PR15355 when CMOV is not availableMichael Liao2013-03-071-6/+22
| | | | | | | | | | | - Phi nodes should be replaced/updated after lowering CMOV into branch because 'mainMBB' updating operand in Phi node is changed. - Add EFLAGS in livein before lowering the 2nd CMOV. It's necessary as we will reuse the EFLAGS generated before the 1st lowered CMOV, which won't clobber EFLAGS. However, we need explicitly specify that. - '-attr=-cmov' test case are added. llvm-svn: 176598
* [mips] Custom-legalize BR_JT.Akira Hatanaka2013-03-062-1/+33
| | | | | | In N64-static, GOT address is needed to compute the branch address. llvm-svn: 176580
* Fix PR15355Michael Liao2013-03-061-102/+182
| | | | | | | | | | | | | - Clear 'mayStore' flag when loading from the atomic variable before the spin loop - Clear kill flag from one use to multiple use in registers forming the address to that atomic variable - don't use a physical register as live-in register in BB (neither entry nor landing pad.) by copying it into virtual register (patch by Cameron Zwarich) llvm-svn: 176538
* [mips] Remove android calling convention.Akira Hatanaka2013-03-054-19/+1
| | | | | | | This calling convention was added just to handle functions which return vector of floats. The fix committed in r165585 solves the problem. llvm-svn: 176530
* [mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 getsAkira Hatanaka2013-03-052-40/+55
| | | | | | returned in registers $2 and $4. llvm-svn: 176527
* [mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctlyAkira Hatanaka2013-03-052-15/+74
| | | | | | handle fp128 returns. llvm-svn: 176523
* [mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floatingAkira Hatanaka2013-03-052-6/+15
| | | | | | point registers. llvm-svn: 176521
* [mips] Correct handling of fp128 (long double) formals and read long doubleAkira Hatanaka2013-03-052-9/+79
| | | | | | parameters from floating point registers if target is mips64 hard float. llvm-svn: 176520
* Add more functions to the TLI.Meador Inge2013-03-051-9/+212
| | | | | | | | | | | This patch adds many more functions to the target library information. All of the functions being added were discovered while doing the migration of the simplify-libcalls attribute annotation functionality to the functionattrs pass. As a part of that work the attribute annotation logic will query TLI to determine if a function should be annotated or not. Signed-off-by: Meador Inge <meadori@codesourcery.com> llvm-svn: 176514
* reverting patch 176508.Jyotsna Verma2013-03-054-28/+0
| | | | llvm-svn: 176513
* Hexagon: Add support for lowering block address.Jyotsna Verma2013-03-054-0/+28
| | | | llvm-svn: 176508
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