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* [mips][FastISel] Implement FastMaterializeAlloca in Mips fast-isel.Vasileios Kalintiris2015-04-171-0/+20
| | | | | | | | | | | | | | | | | | Summary: Implement the method FastMaterializeAlloca in Mips fast-isel Based on a patch by Reed Kotler. Test Plan: Passes test-suite at O0/O2 for mips32 r1/r2 fastalloca.ll Reviewers: dsanders, rkotler Subscribers: rfuhler, llvm-commits Differential Revision: http://reviews.llvm.org/D6742 llvm-svn: 235213
* [X86, AVX] add an exedepfix entry for vmovq == vmovlps == vmovlpdSanjay Patel2015-04-171-1/+1
| | | | | | | | | | This is the AVX extension of r235014: http://llvm.org/viewvc/llvm-project?view=revision&revision=235014 Review: http://reviews.llvm.org/D8691 llvm-svn: 235210
* [mips][FastISel] Implement shift ops for Mips fast-isel.Vasileios Kalintiris2015-04-171-0/+80
| | | | | | | | | | | | | | | | | | Summary: Add shift operators implementation to fast-isel for Mips. These are shift ops for non legal forms, i.e. i8 and i16. Based on a patch by Reed Kotler. Test Plan: Reviewers: dsanders Subscribers: echristo, rfuhler, llvm-commits Differential Revision: http://reviews.llvm.org/D6726 llvm-svn: 235194
* Move AliasedSymbol to MachObjectWriter.Rafael Espindola2015-04-171-2/+2
| | | | | | | It was only used by MachO. Part of pr19627. llvm-svn: 235185
* [mips] Teach the delay slot filler to remove needless KILL instructions.Vasileios Kalintiris2015-04-171-11/+30
| | | | | | | | | | | | | | | | | | Summary: Previously, the presence of KILL instructions would block valid candidates from filling a specific delay slot. With the elimination of the KILL instructions, in the appropriate range, we are able to fill more slots and keep the information from future def/use analysis consistent. Reviewers: dsanders Reviewed By: dsanders Subscribers: hfinkel, llvm-commits Differential Revision: http://reviews.llvm.org/D7724 llvm-svn: 235183
* [mc] Clean up emission of byte sequencesBenjamin Kramer2015-04-174-18/+4
| | | | | | No functional change intended. llvm-svn: 235178
* [mips] Move ABI-dependent register selections to MipsABIInfo. NFC.Daniel Sanders2015-04-176-49/+84
| | | | | | | | | | | | | | | | | | | | | Summary: For example, a common idiom was 'isN64 ? Mips::SP_64 : Mips::SP'. This has been moved to MipsABIInfo and replaced with 'ABI.GetStackPtr()'. There are others that should also be moved. This patch sticks to the ones that are obviously non-functional. The others have minor mistakes that need fixing at the same time, mostly involving checks for 64-bit GPR's instead of checks for 64-bit pointers. Reviewers: tomatabacu Reviewed By: tomatabacu Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8972 llvm-svn: 235173
* [AArch64] Don't assert on f16 in DUP PerfectShuffle generator.Ahmed Bougacha2015-04-161-1/+1
| | | | | | | | Found by code inspection, but breaking i16 at least breaks other tests. They aren't checking this in particular though, so also add some explicit tests for the already working types. llvm-svn: 235148
* Disable AArch64 fast-isel on big-endian call vector returns.Pete Cooper2015-04-161-0/+5
| | | | | | | | A big-endian vector return needs a byte-swap which we aren't doing right now. For now just bail on these cases to get correctness back. llvm-svn: 235133
* [AArch64] Add v8.1a "Virtualization Host Extensions"Vladimir Sukharev2015-04-162-1/+59
| | | | | | | | | | | | Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8500 Patch by: Tom Coxon llvm-svn: 235107
* [AArch64] Add v8.1a "Limited Ordering Regions" extensionVladimir Sukharev2015-04-165-0/+40
| | | | | | | | | | | | Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8499 Patch by: Tom Coxon llvm-svn: 235105
* [AArch64] Add v8.1a "Privileged Access Never" extensionVladimir Sukharev2015-04-162-3/+18
| | | | | | | | | | Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8498 llvm-svn: 235104
* [AArch64] Handle Cyclone-specific register in common wayVladimir Sukharev2015-04-162-29/+5
| | | | | | | | | | | | Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8584 Patch by: Tom Coxon llvm-svn: 235102
* [AArch64] Follow-up to: Refactor AArch64NamedImmMapper to become dependent ↵Vladimir Sukharev2015-04-161-665/+665
| | | | | | | | | | on subtarget features Fixed compilation with clang on some buildbots with "-Werror -Wmissing-field-initializers" Related to: http://reviews.llvm.org/rL235089 llvm-svn: 235099
* [mips] [IAS] Preserve microMIPS label marking for objects when assigning.Toma Tabacu2015-04-161-3/+2
| | | | | | | | | | | | | | Summary: Previously, this was only happening for functions, but because of .insn, objects can also be marked now. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8007 llvm-svn: 235095
* [Mips] Use unique_ptr to manage ownership.Benjamin Kramer2015-04-162-17/+10
| | | | | | | Required some tweaking of ValueMap to accommodate a move-only value type. No functional change intended. llvm-svn: 235091
* Make it obvious that we're iterating over a range of pointers.Benjamin Kramer2015-04-161-1/+1
| | | | | | Found by -Wrange-loop-analysis. llvm-svn: 235090
* [AArch64] Refactor AArch64NamedImmMapper to become dependent on subtarget ↵Vladimir Sukharev2015-04-165-20/+46
| | | | | | | | | | | | | | | | | | | | | | features. In order to introduce v8.1a-specific entities, Mappers should be aware of SubtargetFeatures available. This patch introduces refactoring, that will then allow to easily introduce: - v8.1-specific "pan" PState for PStateMapper (PAN extension) - v8.1-specific sysregs for SysRegMapper (LOR,VHE extensions) Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8496 Patch by Tom Coxon llvm-svn: 235089
* [AArch64] Fix invalid use of references to BuildMI.James Molloy2015-04-161-3/+3
| | | | | | | | This was found in GCC PR65773 (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65773). We shouldn't be taking a reference to the temporary that BuildMI returns, we must copy it. llvm-svn: 235088
* [ARM] Add v8.1a "Privileged Access Never" extensionVladimir Sukharev2015-04-164-3/+99
| | | | | | | | | | Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8504 llvm-svn: 235087
* [mips] [IAS] Add support for the .insn directive.Toma Tabacu2015-04-165-2/+47
| | | | | | | | | | | | | | | | | Summary: This assembler directive marks the current label as an instruction label in microMIPS and MIPS16. This initial implementation works only for microMIPS. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8006 llvm-svn: 235084
* DebugInfo: Gut DIScope, DIEnumerator and DISubrangeDuncan P. N. Exon Smith2015-04-161-3/+3
| | | | | | The only class the still has API left is `DIDescriptor` itself. llvm-svn: 235067
* DebugInfo: Gut DICompileUnit and DIFileDuncan P. N. Exon Smith2015-04-151-3/+3
| | | | | | | Continuing gutting `DIDescriptor` subclasses; this edition, `DICompileUnit` and `DIFile`. In the name of PR23080. llvm-svn: 235055
* Fix BXJ is undefined in AArch32.Charlie Turner2015-04-152-2/+10
| | | | | | | | | | | | | | BXJ was incorrectly said to be unsupported in ARMv8-A. It is not supported in the A64 instruction set, but it is supported in the T32 and A32 instruction sets, because it's listed as an instruction in the ARM ARM section F7.1.28. Using SP as an operand to BXJ changed from UNPREDICTABLE to PREDICTABLE in v8-A. This patch reflects that update as well. This was found by MCHammer. llvm-svn: 235024
* [X86] add an exedepfix entry for movq == movlps == movlpdSanjay Patel2015-04-151-0/+2
| | | | | | | | | | | | | This is a 1-line patch (with a TODO for AVX because that will affect even more regression tests) that lets us substitute the appropriate 64-bit store for the float/double/int domains. It's not clear to me exactly what the difference is between the 0xD6 (MOVPQI2QImr) and 0x7E (MOVSDto64mr) opcodes, but this is apparently the right choice. Differential Revision: http://reviews.llvm.org/D8691 llvm-svn: 235014
* [x86] Implement combineRepeatedFPDivisorsSanjay Patel2015-04-152-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the transform bar at 2 divisions because the fastest current x86 FP divider circuit is in SandyBridge / Haswell at 10 cycle latency (best case) relative to a 5 cycle multiplier. So that's the worst case for this transform (no latency win), but multiplies are obviously pipelined while divisions are not, so there's still a big throughput win which we would expect to show up in typical FP code. These are the sequences I'm comparing: divss %xmm2, %xmm0 mulss %xmm1, %xmm0 divss %xmm2, %xmm0 Becomes: movss LCPI0_0(%rip), %xmm3 ## xmm3 = mem[0],zero,zero,zero divss %xmm2, %xmm3 mulss %xmm3, %xmm0 mulss %xmm1, %xmm0 mulss %xmm3, %xmm0 [Ignore for the moment that we don't optimize the chain of 3 multiplies into 2 independent fmuls followed by 1 dependent fmul...this is the DAG version of: https://llvm.org/bugs/show_bug.cgi?id=21768 ...if we fix that, then the transform becomes even more profitable on all targets.] Differential Revision: http://reviews.llvm.org/D8941 llvm-svn: 235012
* [msp430] Only support the 'm' inline assembly memory constraint. NFC.Daniel Sanders2015-04-151-6/+0
| | | | | | | | | | | | | | Summary: MSP430 doesn't seem to have any additional constraints. Therefore remove the target hook. No functional change intended. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8208 llvm-svn: 235003
* [mips] [IAS] Refactor the function which checks for the availability of AT. NFC.Toma Tabacu2015-04-151-8/+13
| | | | | | | | | | | | | | | | | | Summary: Refactor MipsAsmParser::getATReg to return an internal register number instead of a register index. Also change all the int's to unsigned, seeing as the current AT register index is stored as an unsigned in MipsAssemblerOptions. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8478 llvm-svn: 234996
* [bpf] fix buildAlexei Starovoitov2015-04-155-9/+10
| | | | | | fix build due to refactoring in DIL/MDL and raw_pwrite_stream llvm-svn: 234971
* Change range-based for-loops to be -Wrange-loop-analysis clean.Richard Trieu2015-04-151-1/+1
| | | | | | No functionality change. llvm-svn: 234963
* Use raw_pwrite_stream in the object writer/streamer.Rafael Espindola2015-04-1452-104/+117
| | | | | | The ELF object writer will take advantage of that in the next commit. llvm-svn: 234950
* Correct 'teh' and other typos / repeated words.Ed Maste2015-04-141-1/+1
| | | | | | | | Patch by Eitan Adler. Differential Revision: http://reviews.llvm.org/D8514 llvm-svn: 234939
* Refactor: Simplify boolean expressions in ARM targetAlexander Kornienko2015-04-142-28/+25
| | | | | | | | | | Simplify boolean expressions using `true` and `false` with `clang-tidy` http://reviews.llvm.org/D8524 Patch by Richard Thomson! llvm-svn: 234901
* [AArch64] Allow non-standard INS/DUP encodingsBradley Smith2015-04-142-10/+10
| | | | | | | | | | The ARMv8 ARMARM states that for these instructions in A64 state: "Unspecified bits in "imm5" are ignored but should be set to zero by an assembler.", (imm4 for INS). Make the disassembler accept any encoding with these ignored bits set to 1. llvm-svn: 234896
* R600/SI: Fix verifier error caused by SIAnnotateControlFlowTom Stellard2015-04-141-6/+13
| | | | | | | | | | | | | | This pass will always try to insert llvm.SI.ifbreak intrinsics in the same block that its conditional value is computed in. This is a problem when conditions for breaks or continue are computed outside of the loop, because the llvm.SI.ifbreak intrinsic ends up being inserted outside of the loop. This patch fixes this problem by inserting the llvm.SI.ifbreak intrinsics in the loop header when the condition is computed outside the loop. llvm-svn: 234891
* Re-enable target-specific relocation table sorting and use it for MipsPetar Jovanovic2015-04-141-0/+180
| | | | | | | | | | | | | | Some targets (ie. Mips) have additional rules for ordering the relocation table entries. Allow them to override generic sortRelocs(), which sorts entries by Offset. Then override this function for Mips, to emit HI16 and GOT16 relocations against the local symbol in pair with the corresponding LO16 relocation. Patch by Vladimir Stefanovic. Differential Revision: http://reviews.llvm.org/D7414 llvm-svn: 234883
* DebugInfo: Gut DISubprogram and DILexicalBlock*Duncan P. N. Exon Smith2015-04-141-3/+3
| | | | | | | Gut the `DIDescriptor` wrappers around `MDLocalScope` subclasses. Note that `DILexicalBlock` wraps `MDLexicalBlockBase`, not `MDLexicalBlock`. llvm-svn: 234850
* DebugInfo: Gut DIVariable and DIGlobalVariableDuncan P. N. Exon Smith2015-04-141-2/+2
| | | | | | | | | | Gut all the non-pointer API from the variable wrappers, except an implicit conversion from `DIGlobalVariable` to `DIDescriptor`. Note that if you're updating out-of-tree code, `DIVariable` wraps `MDLocalVariable` (`MDVariable` is a common base class shared with `MDGlobalVariable`). llvm-svn: 234840
* Expand ADDO/SUBO on HexagonKrzysztof Parzyszek2015-04-131-0/+8
| | | | llvm-svn: 234795
* Revert revisions r234755, r234759, r234760Jan Vesely2015-04-137-61/+2
| | | | | | | | | | | Revert "Remove default in fully-covered switch (to fix Clang -Werror -Wcovered-switch-default)" Revert "R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO" Revert "LegalizeDAG: Try to use Overflow operations when expanding ADD/SUB" Using overflow operations fails CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll on hexagon, nvptx, and r600. Revert while I investigate. llvm-svn: 234768
* Allow memory intrinsics to be tail callsKrzysztof Parzyszek2015-04-1310-11/+20
| | | | llvm-svn: 234764
* R600: Add carry and borrow instructions. Use them to implement UADDO/USUBOJan Vesely2015-04-137-2/+61
| | | | | | | | | | | | | | | | v2: tighten the sub64 tests v3: rename to CARRY/BORROW v4: fixup test cmdline add known bits computation use sign extend instead of sub 0,x better add test v5: remove redundant break move lowering to separate functions fix comments Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewers: arsenm llvm-svn: 234759
* R600: Make FMIN/MAXNUM legal on all asicsJan Vesely2015-04-123-2/+7
| | | | | | | | v2: Add tests Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> reviewer: arsenm llvm-svn: 234716
* R600: remove manual BFE optimizationJan Vesely2015-04-121-8/+2
| | | | | | | | Fixed since r233079 Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> reviewer: arsenm llvm-svn: 234715
* [PowerPC] Really iterate over all loops in PPCLoopDataPrefetch/PPCLoopPreIncPrepHal Finkel2015-04-122-14/+6
| | | | | | | | When I fixed these a couple of days ago to iterate over all loops, not just depth == 1 loops, I inadvertently made it such that we'd only look at the first top-level loop. Make sure that we really look at all of them. llvm-svn: 234705
* [PowerPC] Disable part-word atomics on the P7Hal Finkel2015-04-111-2/+2
| | | | | | | As it turns out, even though these are part of ISA 2.06, the P7 does not support them (or, at least, not any P7s we're tested so far). llvm-svn: 234686
* Add direct moves to/from VSR and exploit them for FP/INT conversionsNemanja Ivanovic2015-04-118-1/+134
| | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D8928 It adds direct move instructions to/from VSX registers to GPR's. These are exploited for FP <-> INT conversions. llvm-svn: 234682
* Use 'override/final' instead of 'virtual' for overridden methodsAlexander Kornienko2015-04-1127-29/+31
| | | | | | | | | | | | | | The patch is generated using clang-tidy misc-use-override check. This command was used: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py \ -checks='-*,misc-use-override' -header-filter='llvm|clang' \ -j=32 -fix -format http://reviews.llvm.org/D8925 llvm-svn: 234679
* [PowerPC] Fix PPCLoopPreIncPrep for depth > 1 loopsHal Finkel2015-04-111-10/+27
| | | | | | | | | This pass had the same problem as the data-prefetching pass: it was only checking for depth == 1 loops in practice. Fix that, add some debugging statements, and make sure that, when we grab an AddRec, it is for the loop we expect. llvm-svn: 234670
* [CodeGen] Split -enable-global-merge into ARM and AArch64 options.Ahmed Bougacha2015-04-112-2/+16
| | | | | | | | | | | | | Currently, there's a single flag, checked by the pass itself. It can't force-enable the pass (and is on by default), because it might not even have been created, as that's the targets decision. Instead, have separate explicit flags, so that the decision is consistently made in the target. Keep the flag as a last-resort "force-disable GlobalMerge" for now, for backwards compatibility. llvm-svn: 234666
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