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* Add AVX SSE4.2 instructionsBruno Cardoso Lopes2010-07-071-114/+179
| | | | llvm-svn: 107752
* Use only one multiclass to pinsrq instructionsBruno Cardoso Lopes2010-07-072-38/+20
| | | | llvm-svn: 107750
* Now that almost all SSE4.1 AVX instructions are added, move code around to ↵Bruno Cardoso Lopes2010-07-072-361/+374
| | | | | | more appropriate sections. No functionality changes llvm-svn: 107749
* Add AVX SSE4.1 insertps, ptest and movntdqa instructionsBruno Cardoso Lopes2010-07-071-18/+39
| | | | llvm-svn: 107747
* Add AVX SSE4.1 extractps and pinsr instructionsBruno Cardoso Lopes2010-07-071-35/+67
| | | | llvm-svn: 107746
* Also use REG_SEQUENCE for VTBX instructions.Bob Wilson2010-07-072-24/+30
| | | | llvm-svn: 107743
* Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's whereJim Grosbach2010-07-071-2/+4
| | | | | | they've been tested to work. llvm-svn: 107742
* Add AVX SSE4.1 Extract Integer instructionsBruno Cardoso Lopes2010-07-071-0/+11
| | | | llvm-svn: 107740
* By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing ratherJim Grosbach2010-07-061-0/+2
| | | | | | | than assuming a target will custom lower them. Targets which do so should exlicitly mark them as having custom lowerings. PR7454. llvm-svn: 107734
* Use REG_SEQUENCE nodes to make the table registers for VTBL instructions beBob Wilson2010-07-062-10/+61
| | | | | | allocated to consecutive registers. llvm-svn: 107730
* Accept RIP-relative symbols with 'i' constraint, andDale Johannesen2010-07-062-2/+3
| | | | | | | print the (%rip) only if the 'a' modifier is present. PR 7528. llvm-svn: 107727
* Track defs for all aliases in NEONMoveFix.Jakob Stoklund Olesen2010-07-061-2/+2
| | | | | | | This means that an instruction defining an S register will affect the domain of the parent D register. llvm-svn: 107725
* Add the rest of AVX SSE4.1 packed move with sign/zero extend instructionsBruno Cardoso Lopes2010-07-061-0/+17
| | | | llvm-svn: 107723
* Add part of AVX SSE4.1 packed move with sign/zero extend instructionsBruno Cardoso Lopes2010-07-061-0/+15
| | | | llvm-svn: 107720
* Fix comment from previous patchBruno Cardoso Lopes2010-07-061-1/+1
| | | | llvm-svn: 107717
* Add AVX vblendvpd, vblendvps and vpblendvb instructionsBruno Cardoso Lopes2010-07-064-10/+61
| | | | | | Update VEX encoding to support those new instructions llvm-svn: 107715
* CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.Dan Gohman2010-07-064-6/+6
| | | | | | SelectBasicBlock doesn't needs its BasicBlock argument. llvm-svn: 107712
* Propagate debug loc.Devang Patel2010-07-0615-42/+50
| | | | llvm-svn: 107710
* Represent NEON load/store alignments in bytes, not bits.Bob Wilson2010-07-063-7/+13
| | | | llvm-svn: 107701
* Reapply r107655 with fixes; insert the pseudo instruction intoDan Gohman2010-07-0612-205/+245
| | | | | | | the block before calling the expansion hook. And don't put EFLAGS in a mbb's live-in list twice. llvm-svn: 107691
* Fix PR7545 crash.Devang Patel2010-07-061-3/+3
| | | | llvm-svn: 107678
* Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversionRafael Espindola2010-07-061-4/+6
| | | | | | if profitable. llvm-svn: 107673
* Revert r107655.Dan Gohman2010-07-0612-244/+204
| | | | llvm-svn: 107668
* Make getMinimalPhysRegClass' comment mention what makes it differentDan Gohman2010-07-061-1/+2
| | | | | | from getPhysicalRegisterRegClass. llvm-svn: 107660
* Fix a bunch of custom-inserter functions to handle the case whereDan Gohman2010-07-0612-204/+244
| | | | | | the pseudo instruction is not at the end of the block. llvm-svn: 107655
* Fix up -fstack-protector on linux to use the segmentEric Christopher2010-07-062-0/+27
| | | | | | | | | registers. Split out testcases per architecture and os now. Patch from Nelson Elhage. llvm-svn: 107640
* Have the X86 backend use Triple instead of a string and some enums.Eric Christopher2010-07-053-64/+38
| | | | llvm-svn: 107625
* Remove some unused/redundant code.Kalle Raiskila2010-07-052-20/+0
| | | | llvm-svn: 107622
* more tidying.Chris Lattner2010-07-051-2/+1
| | | | llvm-svn: 107615
* some notes about suboptimal insertps'sChris Lattner2010-07-051-0/+31
| | | | llvm-svn: 107613
* rip out even more sporadic v2f32 support.Chris Lattner2010-07-053-19/+1
| | | | llvm-svn: 107610
* rip out the various v2f32 "mmx" handling logic, now that Chris Lattner2010-07-051-6/+6
| | | | | | v2f32 is illegal on x86. llvm-svn: 107609
* Just rip v2f32 support completely out of the X86 backend. InChris Lattner2010-07-041-23/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the example in the testcase, we now generate: _test1: ## @test1 movss 4(%esp), %xmm0 addss 8(%esp), %xmm0 movl 12(%esp), %eax movss %xmm0, (%eax) ret instead of: _test1: ## @test1 subl $20, %esp movl 24(%esp), %eax movq %mm0, (%esp) movq %mm0, 8(%esp) movss (%esp), %xmm0 addss 12(%esp), %xmm0 movss %xmm0, (%eax) addl $20, %esp ret v2f32 support did not work reliably because most of the X86 backend didn't know it was legal. It was apparently only added to support returning source-level v2f32 values in MMX registers in x86-32 mode. If ABI compatibility is important on this GCC-extended-vector type for some reason, then the frontend should generate IR that returns v2i32 instead of v2f32. However, we generally don't try very hard to be abi compatible on gcc extended vectors. llvm-svn: 107601
* fix PR7518 - terrible codegen of <2 x float>, by only markingChris Lattner2010-07-041-6/+16
| | | | | | | | v2f32 as legal in 32-bit mode. It is just as terrible there, but I just care about x86-64 and noone claims it is valuable in 64-bit mode. llvm-svn: 107600
* indentationChris Lattner2010-07-041-2/+3
| | | | llvm-svn: 107599
* Revert r107583. I no longer think that this is the way to solve the problem.Bill Wendling2010-07-041-2/+2
| | | | llvm-svn: 107585
* Mark sse_load_f32 and sse_load_f64 as having memory operandsBill Wendling2010-07-041-2/+2
| | | | | | | (SDNPMemOperand). This way when they're morphed the memory operands will be copied as well. llvm-svn: 107583
* Minor amendment to switch-lowering improvement.Eli Friedman2010-07-031-2/+10
| | | | llvm-svn: 107569
* Note switch-lowering inefficiency.Eli Friedman2010-07-031-0/+36
| | | | llvm-svn: 107565
* Add AVX SSE4.1 blend, mpsadbw and vdpBruno Cardoso Lopes2010-07-031-0/+19
| | | | llvm-svn: 107560
* Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructionsBruno Cardoso Lopes2010-07-031-0/+26
| | | | llvm-svn: 107558
* Add AVX SSE4.1 Horizontal Minimum and Position instructionBruno Cardoso Lopes2010-07-031-0/+3
| | | | llvm-svn: 107552
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng2010-07-0316-66/+53
| | | | | | slots so it's always false. llvm-svn: 107550
* Add AVX SSE4.1 round instructionsBruno Cardoso Lopes2010-07-031-0/+76
| | | | llvm-svn: 107549
* Simple refactoring of SSE4.1 instructions, making room for the AVX formsBruno Cardoso Lopes2010-07-021-151/+117
| | | | llvm-svn: 107540
* - Add support for the rest of AVX SSE3 instructionsBruno Cardoso Lopes2010-07-022-19/+89
| | | | | | | - Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M represents a REX equivalent two byte leading opcode llvm-svn: 107523
* Remove early IT block formation. It's not used.Evan Cheng2010-07-023-213/+6
| | | | llvm-svn: 107513
* - Two-address pass should not assume unfolding is always successful.Evan Cheng2010-07-021-4/+21
| | | | | | | | | - X86 unfolding should check if the instructions being unfolded has memoperands. If there is no memoperands, then it must assume conservative alignment. If this would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand etc. should not unfold the instruction. llvm-svn: 107509
* beautify outputGabor Greif2010-07-021-0/+1
| | | | llvm-svn: 107500
* use ArgOperand APIGabor Greif2010-07-021-2/+2
| | | | llvm-svn: 107498
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