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* Use uint16_t to store registers in static tables. Matches other tables.Craig Topper2012-05-241-5/+5
| | | | llvm-svn: 157375
* Use uint16_t to store register number in static tables to match other tables.Craig Topper2012-05-241-7/+7
| | | | llvm-svn: 157374
* Make some opcode tables static and const. Allows code to avoid making copies ↵Craig Topper2012-05-241-173/+219
| | | | | | to pass the tables around. llvm-svn: 157373
* Mark a couple arrays as static and const. Use array_lengthof instead of ↵Craig Topper2012-05-242-6/+6
| | | | | | sizeof/sizeof. llvm-svn: 157369
* Mark a static array as const.Craig Topper2012-05-241-1/+1
| | | | llvm-svn: 157368
* Mark a static table as const. Shrink opcode size in static tables to ↵Craig Topper2012-05-241-14/+9
| | | | | | uint16_t. Simplify loop iterating over one of those tables. No functional change intended. llvm-svn: 157367
* Tidy up naming for consistency and other cleanup. No functional change ↵Chad Rosier2012-05-231-10/+9
| | | | | | intended. llvm-svn: 157358
* [arm-fast-isel] Add support for non-global callee.Chad Rosier2012-05-231-7/+17
| | | | | | Patch by Jush Lu <jush.msn@gmail.com>. llvm-svn: 157336
* Tidy up spacing.Craig Topper2012-05-231-2/+2
| | | | llvm-svn: 157313
* Fix indentation of wrapped line for readability. No functional change.Craig Topper2012-05-231-1/+1
| | | | llvm-svn: 157309
* ARMDisassembler.cpp: Fix utf8 char in comments.NAKAMURA Takumi2012-05-221-3/+3
| | | | llvm-svn: 157292
* Fix constant used for pshufb mask when lowering v16i8 shuffles. Bug ↵Craig Topper2012-05-221-1/+1
| | | | | | introduced in r157043. Fixes PR12908. llvm-svn: 157236
* This patch adds a predicate to existing mips32 and mips64 so that thoseAkira Hatanaka2012-05-226-101/+134
| | | | | | | | | | | | | | | | | | | instruction encodings can be excluded during mips16 processing. This revision fixes the issue raised by Jim Grosbach. bool hasStandardEncoding() const { return !inMips16Mode(); } When micromips is added it will be bool StandardEncoding() const { return !inMips16Mode()&& !inMicroMipsMode(); } No additional testing is needed other than to assure that there is no regression from this patch. Patch by Reed Kotler. llvm-svn: 157234
* ARM: .end_data_region mismatch in Thumb2.Jim Grosbach2012-05-211-2/+5
| | | | | | | | | | 32-bit offset jump tables just use real branch instructions and so aren't marked as data regions. We were still emitting the .end_data_region marker though, which assert()ed. rdar://11499158 llvm-svn: 157221
* Thumb2: RSB source register should be rGRP not GPRnopc.Jim Grosbach2012-05-211-4/+4
| | | | | | t2RSB defined the operand correctly, but tRSBS didn't. llvm-svn: 157200
* Allow 256-bit shuffles to still be split even if only half of the shuffle ↵Craig Topper2012-05-211-15/+44
| | | | | | comes from two 128-bit pieces. llvm-svn: 157175
* Make the global base reg GR32_NOSP.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | | | It can sometimes be used in addressing modes that don't support %ESP. llvm-svn: 157165
* Add a missing PPC 64-bit stwu pattern.Hal Finkel2012-05-201-0/+8
| | | | | | | This seems to fix the remaining compile-time failures on PPC64 when compiling with -enable-ppc-preinc. llvm-svn: 157159
* Use the right register class for LDRrs.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | llvm-svn: 157152
* Transfer memory operands to the right instruction.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | | | They need to go on the PICLDR as the verifier points out. llvm-svn: 157151
* Add a FIXME about access to negative stack-pointer offsets on PPC32.Hal Finkel2012-05-191-0/+2
| | | | | | | | | | | | | | The current code will generate a prologue which starts with something like: mflr 0 stw 31, -4(1) stw 0, 4(1) stwu 1, -16(1) But under the PPC32 SVR4 ABI, access to negative offsets from R1 is not allowed. This was pointed out by Peter Bergner. llvm-svn: 157133
* On Haswell, perfer storing YMM registers using a single instruction.Nadav Rotem2012-05-191-5/+4
| | | | llvm-svn: 157129
* Add support for additional in-reg vbroadcast patternsNadav Rotem2012-05-191-3/+9
| | | | llvm-svn: 157127
* Tidy up some spacing and inconsistent use of pre/post increment. No ↵Craig Topper2012-05-192-28/+28
| | | | | | functional change intended. llvm-svn: 157122
* Ordinary PR1255 patch: DifferenceEngine and CPPBackend adopted to the new ↵Stepan Dyatkovskiy2012-05-191-1/+1
| | | | | | SwitchInst methods. llvm-svn: 157112
* Copy some AVX support from MCJIT to JIT. Maybe will fix PR12748.Craig Topper2012-05-191-17/+29
| | | | llvm-svn: 157109
* Add support for the 'd' mips inline asm output modifier.Eric Christopher2012-05-191-12/+17
| | | | | | Patch by Jack Carter. llvm-svn: 157093
* Refactor data-in-code annotations.Jim Grosbach2012-05-184-24/+40
| | | | | | | | | | | | | | | | | | | | | | Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 llvm-svn: 157062
* Add support for the mips 'x' inline asm modifier.Eric Christopher2012-05-181-0/+5
| | | | | | Patch by Jack Carter. llvm-svn: 157057
* Simplify code a bit. No functional change intended.Craig Topper2012-05-181-14/+8
| | | | llvm-svn: 157044
* Simplify handling of v16i8 shuffles and fix a missed optimization.Craig Topper2012-05-181-30/+8
| | | | llvm-svn: 157043
* Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missingKevin Enderby2012-05-173-11/+54
| | | | | | | | | | the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 llvm-svn: 157019
* Remove incorrect pattern for ARM SMML instruction.Tim Northover2012-05-171-2/+1
| | | | | | Patch by Meador Inge. llvm-svn: 156989
* This patch adds the register class for MIPS16 as well as the ability forAkira Hatanaka2012-05-165-11/+26
| | | | | | | | | | | | | | | llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the mips16 ASE for mips32 by default. As part of fixing of adding this we discovered some small changes that need to be made to MipsInstrInfo::storeRegToStackSLot and MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead, per suggestion of Jakob Stoklund Olesen. Patch by Reed Kotler. llvm-svn: 156958
* Hexagon: Remove unused command line option.Benjamin Kramer2012-05-161-2/+0
| | | | llvm-svn: 156917
* Avoid creating a cycle when folding load / op with flag / store. PR11451474. ↵Evan Cheng2012-05-161-0/+14
| | | | | | rdar://11451474 llvm-svn: 156896
* Allow MCCodeEmitter access to the target MCRegisterInfo.Jim Grosbach2012-05-1510-0/+16
| | | | | | | | Add the MCRegisterInfo to the factories and constructors. Patch by Tom Stellard <Tom.Stellard@amd.com>. llvm-svn: 156828
* Temporarily disable anti-dependence breaking for Mips until bug 12829 isAkira Hatanaka2012-05-151-1/+1
| | | | | | resolved. llvm-svn: 156801
* Remove extraneous ';'.Bill Wendling2012-05-151-1/+1
| | | | llvm-svn: 156791
* Add a command line option to skip the delay slot filler pass entirely for Mips.Akira Hatanaka2012-05-141-0/+10
| | | | | | | | | | The purpose of this option is to silence error messages issued by machine verifier passes and enable them to run to the end. If this option is not provided, -verify-machineinstrs complains when it discovers there is a non-terminator instruction (an instruction that is in a delay slot) after the first terminator in a basic block. llvm-svn: 156790
* Fix use of uninitialized variable.David Blaikie2012-05-141-1/+1
| | | | | | Found by GCC's maybe-uninitialized. llvm-svn: 156780
* Revert 156634 upon request until code improvement changes are made.Brendon Cahoon2012-05-1415-3689/+339
| | | | llvm-svn: 156775
* Rename @llvm.debugger to @llvm.debugtrap.Dan Gohman2012-05-141-1/+1
| | | | llvm-svn: 156774
* Hexagon: Initialize TBB to 0.Benjamin Kramer2012-05-131-0/+1
| | | | | | Found by valgrind. llvm-svn: 156744
* Make sure new value jump is enabled for Hexagon V5 as well.Sirish Pande2012-05-121-10/+27
| | | | llvm-svn: 156700
* Support for Hexagon feature, New Value Jump.Sirish Pande2012-05-127-2/+682
| | | | llvm-svn: 156698
* Remove MipsEmitGPRestore.cpp.Akira Hatanaka2012-05-123-99/+0
| | | | llvm-svn: 156696
* Delete all functions that are no longer needed in MipsFunctionInfo, includingAkira Hatanaka2012-05-122-15/+1
| | | | | | | | | the ones that get or set the frame index for the $gp save slot. Remove the piece of code in MipsFunctionInfo::getGlobalBaseReg() which returns GP. This function should always return a virtual register. llvm-svn: 156695
* Stop reserving register $gp. Do not call isGPFI to check whether a frame objectAkira Hatanaka2012-05-121-8/+1
| | | | | | is the $gp save slot. llvm-svn: 156694
* Do not add the pass which restores $gp after every function call.Akira Hatanaka2012-05-121-9/+0
| | | | llvm-svn: 156693
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