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* [NVPTX] emit .file directives for files referenced by subprograms.Artem Belevich2016-02-111-0/+1
| | | | | | | | .. so .loc directives referring to those files work correctly. Differential Revision: http://reviews.llvm.org/D17086 llvm-svn: 260557
* Revert r260507: "[X86] Enable the LEA optimization pass by default."Hans Wennborg2016-02-111-5/+4
| | | | | | This caused PR26575. llvm-svn: 260538
* [AArch64] Refactoring findMatchingStore() in aarch64-ldst-opt; NFCJun Bum Lim2016-02-111-11/+13
| | | | | | | | | | | | Summary: This change makes findMatchingStore() follow the same coding style introduced in r260275. Reviewers: gberry, junbuml Subscribers: aemerson, rengolin, haicheng, bmakam, mssimpso Differential Revision: http://reviews.llvm.org/D17083 llvm-svn: 260534
* [AArch64] Improve load/store optimizer to handle LDUR + LDR.Chad Rosier2016-02-111-11/+68
| | | | | | | | | | | | | This patch allows the mixing of scaled and unscaled load/stores to form load/store pairs. This is a reapplication of r259812, which had an incorrect assert. The test_stur_str_no_assert() test is a reduced version of the issue hit in the AArch64 self-host. PR24465 llvm-svn: 260523
* [X86] Enable the LEA optimization pass by default.Andrey Turetskiy2016-02-111-4/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D16877 llvm-svn: 260507
* [MC][ELF] Handle MIPS specific .sdata and .sbss directivesSimon Atanasyan2016-02-111-0/+26
| | | | | | | | | MIPS specific .sdata and .sbss directives create corresponding sections with proper initialized ELF flags including ELF::SHF_MIPS_GPREL. Differential Revision: http://reviews.llvm.org/D17001 llvm-svn: 260498
* AMDGPU: Fix constant bus use check with subregistersMatt Arsenault2016-02-111-4/+8
| | | | | | | | | | | If the two operands to an instruction were both subregisters of the same super register, it would incorrectly think this counted as the same constant bus use. This fixes the verifier error in fmin_legacy.ll which was missing -verify-machineinstrs. llvm-svn: 260495
* AMDGPU: Fix passes depending on dominator tree for no reasonMatt Arsenault2016-02-112-16/+4
| | | | llvm-svn: 260494
* AMDGPU: Fix not handling new workitem intrinsics in DivergenceAnalysisMatt Arsenault2016-02-111-0/+3
| | | | llvm-svn: 260491
* AMDGPU: Split R600 and SI store loweringMatt Arsenault2016-02-115-90/+89
| | | | | | | These were only sharing some somewhat incorrect logic for when to scalarize or split vectors. llvm-svn: 260490
* [AMDGPU] Assembler: Fix VOP3 only instructionsTom Stellard2016-02-114-92/+145
| | | | | | | | | | | | | | | | | | | | | Separate methods to convert parsed instructions to MCInst: - VOP3 only instructions (always create modifiers as operands in MCInst) - VOP2 instrunctions with modifiers (create modifiers as operands in MCInst when e64 encoding is forced or modifiers are parsed) - VOP2 instructions without modifiers (do not create modifiers as operands in MCInst) - Add VOP3Only flag. Pass HasMods flag to VOP3Common. - Simplify code that deals with modifiers (-1 is now same as 0). This is no longer needed. - Add few tests (more will be added separately). Update error message now correct. Patch By: Nikolay Haustov Differential Revision: http://reviews.llvm.org/D16778 llvm-svn: 260483
* [WebAssembly] Re-triage list of compilation failures for torture testsDerek Schuff2016-02-101-52/+39
| | | | llvm-svn: 260438
* [codeview] Describe int local variables using .cv_def_rangeReid Kleckner2016-02-103-5/+45
| | | | | | | | | | | | | | | | Summary: Refactor common value, scope, and label tracking logic out of DwarfDebug into a common base class called DebugHandlerBase. Update an old LLVM IR test case to avoid an assertion in LexicalScopes. Reviewers: dblaikie, majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D16931 llvm-svn: 260432
* [WebAssembly] Address comments left over from r260421Derek Schuff2016-02-102-8/+10
| | | | llvm-svn: 260429
* AMDGPU: Release the scavenged offset register during VGPR spillNicolai Haehnle2016-02-101-1/+8
| | | | | | | | | | | | | | | | | | | Summary: This fixes a crash where subsequent spills would be unable to scavenge a register. In particular, it fixes a crash in piglit's spec@glsl-1.50@execution@geometry@max-input-components (the test still has a shader that fails to compile because of too many SGPR spills, but at least it doesn't crash any more). This is a candidate for the release branch. Reviewers: arsenm, tstellarAMD Subscribers: qcolombet, arsenm Differential Revision: http://reviews.llvm.org/D16558 llvm-svn: 260427
* [x86] refactor masked load/store combine logic ; NFCISanjay Patel2016-02-101-27/+36
| | | | llvm-svn: 260426
* [WebAssembly] Switch varags calling convention to use a registerDerek Schuff2016-02-104-107/+62
| | | | | | | | | | | | Instead of passing varargs directly on the user stack, allocate a buffer in the caller's stack frame and pass a pointer to it. This simplifies the C ABI (e.g. non-C callers of C functions do not need to use C's user stack if they have their own mechanism) and allows further optimizations in the future (e.g. fewer functions may need to use the stack). Differential Revision: http://reviews.llvm.org/D17048 llvm-svn: 260421
* [AArch64] Refactor is logic into a helper function. NFC.Chad Rosier2016-02-101-12/+22
| | | | llvm-svn: 260419
* [AArch64] Update comment to match reality. NFC.Chad Rosier2016-02-101-2/+2
| | | | llvm-svn: 260406
* [MC] Merge VK_PPC_TPREL in to generic VK_TPREL.Colin LeMahieu2016-02-104-28/+28
| | | | | | Differential Revision: http://reviews.llvm.org/D17038 llvm-svn: 260401
* AMDGPU: Fix indentation and variable namesMatt Arsenault2016-02-101-34/+31
| | | | llvm-svn: 260399
* AMDGPU: Split R600 and SI load loweringMatt Arsenault2016-02-105-103/+95
| | | | | | | These weren't actually sharing anything in the common LowerLOAD. llvm-svn: 260398
* [SPARC] Repair floating-point condition encodings in assembly parser.James Y Knight2016-02-101-3/+3
| | | | | | | | | | | | | | | The encodings for floating point conditions A(lways) and N(ever) were incorrectly specified for the assembly parser, per Sparc manual v8 page 121. This change corrects that mistake. Also, strangely, all of the branch instructions already had MC test cases, except for the broken ones. Added the tests. Patch by Chris Dewhurst Differential Revision: http://reviews.llvm.org/D17074 llvm-svn: 260390
* [AArch64] This bit of logic is specific to pairing. NFC.Chad Rosier2016-02-101-8/+10
| | | | llvm-svn: 260383
* [X86] Fix stack alignment for MCU target, by Anton Nadolskiy.Andrey Turetskiy2016-02-101-2/+7
| | | | | | | | This patch fixes stack alignments for MCU (should be aligned to 4 bytes). Differential Revision: http://reviews.llvm.org/D15646 llvm-svn: 260375
* [AVR] Add instruction definitionsDylan McKay2016-02-105-3/+2569
| | | | | | | | | | | | Summary: Add the AVR instruction tablegen definitions. Reviewers: stoklund, hfinkel, dsanders, arsenm, vkalintiris Subscribers: dylanmckay, agnat, rjordans, llvm-commits Differential Revision: http://reviews.llvm.org/D15703 llvm-svn: 260363
* X86: Remove useless semicolonJF Bastien2016-02-101-1/+1
| | | | llvm-svn: 260359
* [x86] convert masked load of exactly one element to scalar loadSanjay Patel2016-02-091-0/+43
| | | | | | | This is the load counterpart to the store optimization that was added in: http://reviews.llvm.org/rL260145 llvm-svn: 260325
* [CodeGen] Prefer "if (SDValue R = ...)" to "if (R.getNode())". NFCI.Ahmed Bougacha2016-02-0910-117/+64
| | | | llvm-svn: 260316
* [X86] Don't reuse an unrelated variable, create a new one. NFC.Ahmed Bougacha2016-02-091-26/+28
| | | | | | | Using Op makes it look like we're doing something with it. We're really not. llvm-svn: 260315
* [X86] Remove unnecessary assignment. NFC.Ahmed Bougacha2016-02-091-1/+0
| | | | llvm-svn: 260314
* [mips] Extend MipsAsmParser class to handle %got(sym + const) expressionsSimon Atanasyan2016-02-091-0/+1
| | | | | | | | | Now the parser supports `%got(sym)` expressions only but `%got(sym + const)` variant is also valid and accepted by GAS. Differential Revision: http://reviews.llvm.org/D16885 llvm-svn: 260305
* [SelectionDAG] make getMemBasePlusOffset() accessible; NFCISanjay Patel2016-02-091-38/+23
| | | | | | | | | I reinvented this functionality in http://reviews.llvm.org/D16828 because it was hidden away as a static function. The changes in x86 are not based on a complete audit. I suspect there are other possible uses there, and there are almost certainly more potential users in other targets. llvm-svn: 260295
* [AArch64] This check is specific to merging instructions. NFC.Chad Rosier2016-02-091-4/+4
| | | | llvm-svn: 260283
* [AArch64] AArch64LoadStoreOptimizer: fix bug in pre-inc check iteratorGeoff Berry2016-02-091-8/+9
| | | | | | | | | | | | | | | Summary: Fix case where a pre-inc/dec load/store would not be formed if the add/sub that forms the inc/dec part of the operation was the first instruction in the block being examined. Reviewers: mcrosier, jmolloy, t.p.northover, junbuml Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D16785 llvm-svn: 260275
* [AArch64] Bail even earlier if the instructions modifieds the base register. ↵Chad Rosier2016-02-091-5/+6
| | | | | | NFC. llvm-svn: 260274
* [AArch64] Simplify. NFC.Chad Rosier2016-02-091-3/+1
| | | | llvm-svn: 260273
* [AArch64] Add an assert to ensure we don't scale an offset that can't be scaled.Chad Rosier2016-02-091-1/+3
| | | | llvm-svn: 260272
* [AArch64] Add a FIXME about invalid KILL markers after the ld/st opt pass.Chad Rosier2016-02-091-0/+5
| | | | llvm-svn: 260264
* [AArch64] Remove redundant calls and clang format. NFC.Chad Rosier2016-02-091-42/+40
| | | | llvm-svn: 260260
* [Hexagon] Fixing relocation generation and adding tests.Colin LeMahieu2016-02-092-182/+263
| | | | llvm-svn: 260259
* [AArch64] Hoist now common logic. NFC.Chad Rosier2016-02-091-13/+9
| | | | llvm-svn: 260257
* [AArch64] Rename variable to make it clear we're merging here, not pairing.Chad Rosier2016-02-091-19/+19
| | | | llvm-svn: 260256
* [AArch64] Separage the codegen logic for widening vs. pairing. NFC.Chad Rosier2016-02-091-38/+94
| | | | llvm-svn: 260249
* [AArch64] Cleanup to simplify logic when widening vs. pairing loads/stores. NFC.Chad Rosier2016-02-091-13/+50
| | | | | | | | The logic to pair instructions and merge narrow instructions has become cloogy and error prone. This patch beings to unravel these two similar, but distinct optimizations. llvm-svn: 260242
* [x86] make getOneTrueElt() a helper function ; NFCSanjay Patel2016-02-091-35/+34
| | | | | | | As mentioned in http://reviews.llvm.org/D16828 , the related masked load transform will need this logic, so I'm moving it out to make that patch smaller. llvm-svn: 260240
* [AArch64] Rename variable to improve readability. NFC.Chad Rosier2016-02-091-5/+5
| | | | llvm-svn: 260228
* [AArch64] Remove stale comment.Chad Rosier2016-02-091-3/+0
| | | | llvm-svn: 260226
* [X86][AVX2] Fix SIGN_EXTEND vector handling on AVX2 targets.Simon Pilgrim2016-02-091-6/+20
| | | | | | | | | | On AVX2 target we are poorly legalizing SIGN_EXTEND ops for which the input's legalized type doesn't have the same number of elements as the destination, resulting in an ANY_EXTEND followed by a SIGN_EXTEND_INREG. This patch uses the existing SIGN_EXTEND -> SIGN_EXTEND_VECTOR_INREG combine to extend the input to the size of the result and using SIGN_EXTEND_VECTOR_INREG instead. Differential Revision: http://reviews.llvm.org/D16994 llvm-svn: 260210
* [X86][SSE1] Add MOVLHPS/MOVHLPS lowering and memory folding supportSimon Pilgrim2016-02-082-0/+29
| | | | | | | | | | As discussed on PR26491, this patch adds support for lowering v4f32 shuffles to the MOVLHPS/MOVHLPS instructions. It also adds support for memory folding with their MOVLPS/MOVHPS load equivalents. This first patch only really helps SSE1 targets as SSE2+ targets will widen the shuffle mask and use v2f64 equivalents (although they still combine to MOVLHPS/MOVHLPS for v2f64 splats). This will have to be addressed in a future patch, most likely when we add support for binary target shuffle combines. Differential Revision: http://reviews.llvm.org/D16956 llvm-svn: 260168
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