summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* IR: Give 'DI' prefix to debug info metadataDuncan P. N. Exon Smith2015-04-292-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Finish off PR23080 by renaming the debug info IR constructs from `MD*` to `DI*`. The last of the `DIDescriptor` classes were deleted in r235356, and the last of the related typedefs removed in r235413, so this has all baked for about a week. Note: If you have out-of-tree code (like a frontend), I recommend that you get everything compiling and tests passing with the *previous* commit before updating to this one. It'll be easier to keep track of what code is using the `DIDescriptor` hierarchy and what you've already updated, and I think you're extremely unlikely to insert bugs. YMMV of course. Back to *this* commit: I did this using the rename-md-di-nodes.sh upgrade script I've attached to PR23080 (both code and testcases) and filtered through clang-format-diff.py. I edited the tests for test/Assembler/invalid-generic-debug-node-*.ll by hand since the columns were off-by-three. It should work on your out-of-tree testcases (and code, if you've followed the advice in the previous paragraph). Some of the tests are in badly named files now (e.g., test/Assembler/invalid-mdcompositetype-missing-tag.ll should be 'dicompositetype'); I'll come back and move the files in a follow-up commit. llvm-svn: 236120
* [mips][microMIPSr6] Implement SUB and SUBU instructionsZoran Jovanovic2015-04-291-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D8764 llvm-svn: 236118
* [mips][microMIPSr6] Implement ADD, ADDU and ADDIU instructionsZoran Jovanovic2015-04-293-5/+43
| | | | | | Differential Revision: http://reviews.llvm.org/D8704 llvm-svn: 236111
* Sparc: Prefer reg+reg address encoding when only one register used.James Y Knight2015-04-291-5/+5
| | | | | | | | | | | Reg+%g0 is preferred to Reg+imm0 by the manual, and is what GCC produces. Futhermore, reg+imm is invalid for the (not yet supported) "alternate address space" instructions. Differential Revision: http://reviews.llvm.org/D8753 llvm-svn: 236107
* Mips fast-isel - handle functions which return i8 or i6 .Vasileios Kalintiris2015-04-292-8/+12
| | | | | | | | | | | | | | | | Summary: Allow Mips fast-isel to handle functions which return i8/i16 signed/unsigned. Test Plan: Make check tests are forthcoming. Already passes test-suite at O0/O2 for Mips 32 r1/r2 Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6765 llvm-svn: 236103
* [mips] Correct 128-bit shifts on 64-bit targets.Daniel Sanders2015-04-291-5/+5
| | | | | | | | | | | | | | | | Summary: The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now accounts for both cases. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits, mohit.bhakkad, sagar Differential Revision: http://reviews.llvm.org/D9337 llvm-svn: 236099
* [mips] [IAS] Inline assemble-time shifting out of createLShiftOri. NFC.Toma Tabacu2015-04-291-15/+24
| | | | | | | | | | | | | | | | Summary: Do the assemble-time shifts from createLShiftOri at the source, which groups all the shifting together, closer to the main logic path, and store the results in concisely-named variables to improve code clarity. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8973 llvm-svn: 236096
* fixed 80-chars; NFCElena Demikhovsky2015-04-291-5/+7
| | | | llvm-svn: 236093
* Reuse a lookup in an assert.Eric Christopher2015-04-281-3/+3
| | | | llvm-svn: 236054
* ARM: fix peephole optimisation of TSTTim Northover2015-04-281-10/+0
| | | | | | | | | | | We were trying to look through COPY instructions, but only to the next instruction in a BB and incorrectly anyway. The cases where that would actually be a good idea are rare enough (and not even tested!) that it's not worth trying to get right. rdar://20721342 llvm-svn: 236050
* Sparc: Add alternate aliases for conditional branch instructions.James Y Knight2015-04-281-0/+6
| | | | llvm-svn: 236042
* [bpf] fix buildAlexei Starovoitov2015-04-282-8/+9
| | | | | | Patch by Brenden Blanco. llvm-svn: 236030
* [x86] remove RCPPS and RSQRTPS intrinsic instruction definitionsSanjay Patel2015-04-283-52/+6
| | | | | | | | | | | | | We don't need codegen-only intrinsic instructions for the vector forms of these instructions. This makes the reciprocal estimate instruction lowering identical to how we handle normal square roots: (V)SQRTPS / (V)SQRTPD. No existing regression tests fail with this patch. Differential Revision: http://reviews.llvm.org/D9301 llvm-svn: 236013
* Add a fixme to resetTargetOptions to explain why it needs to goEric Christopher2015-04-281-0/+5
| | | | | | away. llvm-svn: 236009
* Fix a [-Werror,-Winconsistent-missing-override] problem in theEric Christopher2015-04-281-1/+1
| | | | | | NVPTX overrides. llvm-svn: 236007
* R600: Fix up for AsmPrinter's OutStreamer being a unique_ptrTom Stellard2015-04-281-2/+3
| | | | | | | | | | | Fixes a crash with basically any OpenGL application using the radeonsi driver. Patch by: Michel Dänzer Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90176 Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 236004
* R600/SI: Add a lower case alias for subtarget feature: +DumpCodeTom Stellard2015-04-281-0/+5
| | | | | | | llc converts all feature strings to lower case, while the LLVM C API does not, so we need a lower case alias in order to test this with llc. llvm-svn: 236003
* [NVPTX] Handle addrspacecast constant expressions in aggregate initializersJustin Holewinski2015-04-284-2/+268
| | | | | | | | | | | We need to track if an AddrSpaceCast expression was seen when generating an MCExpr for a ConstantExpr. This change introduces a custom lowerConstant method to the NVPTX asm printer that will create NVPTXGenericMCSymbolRefExpr nodes at the appropriate places to encode the information that a given symbol needs to be casted to a generic address. llvm-svn: 236000
* move IR-level optimization flags into their own structSanjay Patel2015-04-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | This is a preliminary step to using the IR-level floating-point fast-math-flags in the SDAG (D8900). In this patch, we introduce the optimization flags as their own struct. As noted in the TODO comment, we should eventually share this data between the IR passes and the backend. We also switch the existing nsw / nuw / exact bit functionality of the BinaryWithFlagsSDNode class to use the new struct. The tradeoff is that instead of using the free but limited space of SDNode's SubclassData, we add a data member to the subclass. This means we don't have to repeat all of the get/set methods per flag, but we're potentially adding size to all nodes of this subclassi type. In practice on 64-bit systems (measured on Linux and MacOS X), there is no size difference between an SDNode and BinaryWithFlagsSDNode after this change: they're both 80 bytes. This means that we had at least one free byte to play with due to struct alignment. Differential Revision: http://reviews.llvm.org/D9325 llvm-svn: 235997
* Fixed crash of variable shift inst on AVX2Elena Demikhovsky2015-04-281-3/+1
| | | | | | https://llvm.org/bugs/show_bug.cgi?id=22955 llvm-svn: 235993
* [mips] [IAS] Do not generate redundant ORi in createLShiftOri.Toma Tabacu2015-04-281-0/+4
| | | | | | | | | | | | | | Summary: If the immediate is 0, the ORi is pointless. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8969 llvm-svn: 235990
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-2859-2509/+2837
| | | | | | | | | | | | | | | | | | | | | | | | | [DebugInfo] Add debug locations to constant SD nodes This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235989
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-2859-2837/+2509
| | | | | | | This breaks a test: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870 llvm-svn: 235987
* [mips] [IAS] Rename the createShiftOr function to createLShiftOri. NFC.Toma Tabacu2015-04-281-13/+13
| | | | | | | | | | | | | | Summary: The new name is more accurate with regard to the functionality. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8968 llvm-svn: 235984
* [mips] [IAS] Store the expandLoadImm destination register in a variable. NFC.Toma Tabacu2015-04-281-11/+12
| | | | | | | | | | | | | | Summary: This removes multiple calls to getReg() and saves us column space in the source file. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8924 llvm-svn: 235978
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-2859-2509/+2837
| | | | | | | | | | | | | | | | | | | | | | | This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235977
* AVX-512: Added "pandn" intrinsics setElena Demikhovsky2015-04-281-0/+6
| | | | | | by Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 235971
* [MC] Use LShr for constant evaluation of ">>" on ELF/arm64--darwin.Ahmed Bougacha2015-04-281-0/+4
| | | | | | | | | | This matches other assemblers and is less unexpected (e.g. PR23227). On ELF, I tried binutils gas v2.24 and nasm 2.10.09, and they both agree on LShr. On COFF, I couldn't get my hands on an assembler yet, so don't change the behavior. For now, don't change it on non-AArch64 Darwin either, as the other assembler is gas v1.38, which does an AShr. llvm-svn: 235963
* Cleanup, remove unused return valueMatthias Braun2015-04-282-6/+3
| | | | llvm-svn: 235952
* remove obsolete pattern matches for scalar SSE opsSanjay Patel2015-04-271-15/+1
| | | | | | | | The blendi pattern should always replace the insertps pattern after: http://reviews.llvm.org/rL232850 http://reviews.llvm.org/rL235124 llvm-svn: 235930
* [AArch64] Also combine vector selects fed by non-i1 SETCCs.Ahmed Bougacha2015-04-271-3/+15
| | | | | | | | | | | | | | After legalization, scalar SETCC has an i32 result type on AArch64. The i1 requirement seems too conservative, replace it with an assert. This also means that we now can run after legalization. That should also be fine, since the ops legalizer runs again after each combine, and all types created all have the same sizes as the (legal) inputs. Exposed by r235917; while there, robustize its tests (bsl also uses the register it defines). llvm-svn: 235922
* [AArch64] Don't assert when combining (v3f32 select (setcc f64)).Ahmed Bougacha2015-04-271-0/+6
| | | | | | | | When the setcc has f64 operands, we can't build a vector setcc mask to feed a vselect, because f64 doesn't divide v3f32 evenly. Just bail out when that happens. llvm-svn: 235917
* Silence unused variable errors for no-asserts buildsBill Schmidt2015-04-271-0/+4
| | | | llvm-svn: 235913
* [PPC64LE] Remove unnecessary swaps from lane-insensitive vector computationsBill Schmidt2015-04-276-0/+824
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a new SSA MI pass that runs on little-endian PPC64 code with VSX enabled. Loads and stores of 4x32 and 2x64 vectors without alignment constraints are accomplished for little-endian using lxvd2x/xxswapd and xxswapd/stxvd2x. The existence of the additional xxswapd instructions hurts performance in comparison with big-endian code, but they are necessary in the general case to support correct semantics. However, the general case does not apply to most vector code. Many vector instructions are lane-insensitive; they do not "care" which lanes the parallel computations are performed within, provided that the resulting data is stored into the correct locations. Thus this pass looks for computations that perform only lane-insensitive operations, and remove the unnecessary swaps from loads and stores in such computations. Future improvements will allow computations using certain lane-sensitive operations to also be optimized in this manner, by modifying the lane-sensitive operations to account for the permuted order of the lanes. However, this patch only adds the infrastructure to permit this; no lane-sensitive operations are optimized at this time. This code is heavily exercised by the various vectorizing applications in the projects/test-suite tree. For the time being, I have only added one simple test case to demonstrate what the pass is doing. Although it is quite simple, it provides coverage for much of the code, including the special case handling of copies and subreg-to-reg operations feeding the swaps. I plan to add additional tests in the future as I fill in more of the "special handling" code. Two existing tests were affected, because they expected the swaps to be present, but they are now removed. llvm-svn: 235910
* fix 80-cols; NFCSanjay Patel2015-04-271-2/+3
| | | | llvm-svn: 235902
* fix typos; NFCSanjay Patel2015-04-271-1/+1
| | | | llvm-svn: 235896
* [mips] Correct bytes to bits in 2 comments. NFC.Toma Tabacu2015-04-271-2/+2
| | | | llvm-svn: 235891
* AVX-512: added calling conventions for i1 vectors.Elena Demikhovsky2015-04-272-3/+27
| | | | | | Fixed bug: https://llvm.org/bugs/show_bug.cgi?id=20724 llvm-svn: 235889
* [Hexagon] Use constant extenders to fix up hardware loopsBrendon Cahoon2015-04-276-72/+114
| | | | | | | | | | Use a loop instruction with a constant extender for a hardware loop instruction that is too far away from the start of the loop. This is cheaper than changing the SA register value. Differential Revision: http://reviews.llvm.org/D9262 llvm-svn: 235882
* [mips] [IAS] Improve warning for using AT with .set noat.Toma Tabacu2015-04-271-12/+7
| | | | | | | | | | | | | | | | | Summary: Changed the warning message to show the current value of $at, similar to what clang does for typedef's, and renamed warnIfAssemblerTemporary to a more descriptive name. I also changed the type of variables which store registers from int to unsigned, updated the relevant test and tried to make the related comments clearer. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8479 llvm-svn: 235881
* Reapply "[mips][FastISel] Implement shift ops for Mips fast-isel.""Vasileios Kalintiris2015-04-271-0/+80
| | | | | | | | This reapplies r235194, which was reverted in r235495 because it was causing a failure in our out-of-tree buildbots for MIPS. With the sign-extension patch in r235718, this patch doesn't cause any problem any more. llvm-svn: 235878
* [mips] [IAS] Rename getATRegNum and setATReg to {g,s}etATRegIndex. NFC.Toma Tabacu2015-04-271-8/+8
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8480 llvm-svn: 235877
* AVX-512: Extend/Truncate operations for SKX,Elena Demikhovsky2015-04-272-36/+139
| | | | | | SETCC for bit-vectors llvm-svn: 235875
* [X86][SSE] Add v16i8/v32i8 multiplication supportSimon Pilgrim2015-04-271-4/+78
| | | | | | | | | | Patch to allow int8 vectors to be multiplied on the SSE unit instead of being scalarized. The patch sign extends the i8 lanes to i16, uses the SSE2 pmullw multiplication instruction, then packs the lower byte from each result. Differential Revision: http://reviews.llvm.org/D9115 llvm-svn: 235837
* [bpf] fix build and remove a compiler warning in Release modeAlexei Starovoitov2015-04-262-1/+3
| | | | | | Patch by Brenden Blanco. llvm-svn: 235814
* [ARM] Simplify code. NFC.Benjamin Kramer2015-04-251-15/+2
| | | | llvm-svn: 235803
* [hexagon] Use range-based for loops. No functionality change intended.Benjamin Kramer2015-04-251-69/+45
| | | | llvm-svn: 235802
* [hexagon] Remove setHexLibcallName, it leaks memory.Benjamin Kramer2015-04-252-79/+83
| | | | | | | Just spell out the full names, it's not that much more code. No functional change intended. llvm-svn: 235801
* [AsmPrinter] Make AsmPrinter's OutStreamer member a unique_ptr.Lang Hames2015-04-2415-523/+528
| | | | | | | AsmPrinter owns the OutStreamer, so an owning pointer makes sense here. Using a reference for this is crufty. llvm-svn: 235752
* [mips][FastISel] Specify which types we handle for integer extension.Vasileios Kalintiris2015-04-241-0/+7
| | | | | | | | | | | | | | | | | | Summary: Perform integer extension only when the destination type is one of i8, i16 & i32 and when the source type is i1, i8 or i16. For other combinations we fall back to SelectionDAG. This fixes the test MultiSource/Benchmarks/7zip that was failing in our out-of-tree MIPS buildbots. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9243 llvm-svn: 235718
OpenPOWER on IntegriCloud