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* Bump SmallString to the minimum required amount for raw_ostream to avoid ↵Benjamin Kramer2015-05-231-1/+1
| | | | | | | | allocation. NFC. llvm-svn: 238104
* [Mips] Prefer Twine::utohexstr over utohexstr, saves a string copy.Benjamin Kramer2015-05-231-3/+2
| | | | | | NFC. llvm-svn: 238103
* [AArch64] Clean up the ELF streamer a bit.Benjamin Kramer2015-05-232-15/+4
| | | | llvm-svn: 238102
* [AArch64] Move AArch64TargetStreamer out of MCStreamer.hBenjamin Kramer2015-05-234-6/+47
| | | | | | It doesn't belong in the shared MC layer. NFC. llvm-svn: 238101
* [PowerPC] Fix fast-isel when compare is split from branchHal Finkel2015-05-231-19/+32
| | | | | | | | | | | When the compare feeding a branch was in a different BB from the branch, we'd try to "regenerate" the compare in the block with the branch, possibly trying to make use of values not available there. Copy a page from AArch64's play book here to fix the problem (at least in terms of correctness). Fixes PR23640. llvm-svn: 238097
* Stop resetting NoFramePointerElim in TargetMachine::resetTargetOptions.Akira Hatanaka2015-05-236-17/+21
| | | | | | | | | | | | | | This is part of the work to remove TargetMachine::resetTargetOptions. In this patch, instead of updating global variable NoFramePointerElim in resetTargetOptions, its use in DisableFramePointerElim is replaced with a call to TargetFrameLowering::noFramePointerElim. This function determines on a per-function basis if frame pointer elimination should be disabled. There is no change in functionality except that cl:opt option "disable-fp-elim" can now override function attribute "no-frame-pointer-elim". llvm-svn: 238080
* Revert "make reciprocal estimate code generation more flexible by adding ↵Rafael Espindola2015-05-237-267/+54
| | | | | | | | | | | | command-line options" This reverts commit r238051. It broke some bots: http://lab.llvm.org:8011/builders/llvm-ppc64-linux1/builds/18190 llvm-svn: 238075
* make reciprocal estimate code generation more flexible by adding ↵Sanjay Patel2015-05-227-54/+267
| | | | | | | | | | | | | | | | command-line options This patch adds a class for processing many recip codegen possibilities. The TargetRecip class is intended to handle both command-line options to llc as well as options passed in from a front-end such as clang with the -mrecip option. The x86 backend is updated to use the new functionality. Only -mcpu=btver2 with -ffast-math should see a functional change from this patch. All other CPUs continue to *not* use reciprocal estimates by default with -ffast-math. Differential Revision: http://reviews.llvm.org/D8982 llvm-svn: 238051
* Use new MachineInstr mayLoadOrStore() API. NFC.Chad Rosier2015-05-222-3/+2
| | | | llvm-svn: 238044
* [bpf] emit jmp fixups in little endianAlexei Starovoitov2015-05-221-1/+3
| | | | | | | | The 'off' field of 'struct bpf_insn' is in cpu-endianness, since the rest is emitted as little endian, make sure that 'off' field is little endian as well. llvm-svn: 238038
* Reapply r238011 with a fix for the trap instruction.Quentin Colombet2015-05-227-110/+249
| | | | | | | | | | | | | | | | | | | The problem was that I slipped a change required for shrink-wrapping, namely I used getFirstTerminator instead of the getLastNonDebugInstr that was here before the refactoring, whereas the surrounding code is not yet patched for that. Original message: [X86] Refactor the prologue emission to prepare for shrink-wrapping. - Add a late pass to expand pseudo instructions (tail call and EH returns). Instead of doing it in the prologue emission. - Factor some static methods in X86FrameLowering to ease code sharing. NFC. Related to <rdar://problem/20821487> llvm-svn: 238035
* [PPC64] Add support for clrbhrb, mfbhrbe, rfebb.Bill Schmidt2015-05-227-0/+82
| | | | | | | | | | | This patch adds support for the ISA 2.07 additions involving the branch history rolling buffer and event-based branching. These will not be used by typical applications, so built-in support is not required. They will only be available via inline assembly. Assembly/disassembly tests are included in the patch. llvm-svn: 238032
* [ARM] Fix typo in subtarget feature list for 7em tripleJohn Brawn2015-05-221-1/+1
| | | | | | | | | | | The list of subtarget features for the 7em triple contains 't2xtpk', which actually disables that subtarget feature. Correct that to '+t2xtpk' and test that the instructions enabled by that feature do actually work. Differential Revision: http://reviews.llvm.org/D9936 llvm-svn: 238022
* Revert "[X86] Fix a variable name for r237977 so that it works with every ↵Tamas Berghammer2015-05-227-250/+111
| | | | | | | | | | | compilers." Revert "[X86] Refactor the prologue emission to prepare for shrink-wrapping." This reverts commit 6b3b93fc8b68a2c806aa992ee4bd3d7f61898d4b. This reverts commit ab0b15dff8539826283a59c2dd700a18a9680e0f. llvm-svn: 238011
* [X86] Fix a variable name for r237977 so that it works with every compilers.Quentin Colombet2015-05-221-3/+3
| | | | llvm-svn: 237980
* [X86] Refactor the prologue emission to prepare for shrink-wrapping.Quentin Colombet2015-05-227-111/+250
| | | | | | | | | | | | - Add a late pass to expand pseudo instructions (tail call and EH returns). Instead of doing it in the prologue emission. - Factor some static methods in X86FrameLowering to ease code sharing. NFC. Related to <rdar://problem/20821487> llvm-svn: 237977
* [PPC] Correct iterator bug in PPCTLSDynamicCallHal Finkel2015-05-211-2/+4
| | | | | | | | | | | | Unfortunately, I can't reduce a small test case for this (although compiling mpfr-3.1.2 with -O2 -mcpu=a2 would fairly reliably trigger a crash), but the problem is fairly clear (at least once you know you're looking for one). If the TLS instruction being replaced was at the end of the block, we'd increment the iterator past it (so it would then point to MBB.end()), and then we'd increment it again as part of the for statement, thus overrunning the end of the list. Don't do that. llvm-svn: 237974
* Revert r237590, "ARM: allow jump tables to be placed as constant islands."Peter Collingbourne2015-05-217-312/+170
| | | | | | | Caused a miscompile of the Android port of Chromium, details forthcoming. llvm-svn: 237972
* Use new MachineInstr mayLoadOrStore() API.Chad Rosier2015-05-212-5/+3
| | | | llvm-svn: 237965
* [AArch64] Enhance the load/store optimizer with target-specific alias analysis.Chad Rosier2015-05-211-20/+51
| | | | | Phabricator: http://reviews.llvm.org/D9863 llvm-svn: 237963
* [opaque pointer type] Allow gep_type_iterator to work with the pointee type ↵David Blaikie2015-05-212-0/+2
| | | | | | | | | | | from the GEP instruction The raw non-instruction/constant form of this is still relying on being able to access the pointee type from a pointer type - those will be cleaned up later. For now, just focus on the cases where the pointee type is easily accessible. llvm-svn: 237958
* Stop forwarding (get|set)Aligment from MCSectionData to MCSection.Rafael Espindola2015-05-212-16/+17
| | | | llvm-svn: 237956
* [PPC64] Handle vpkudum mask pattern correctly when vpkudum isn't availableBill Schmidt2015-05-211-1/+8
| | | | | | | | | | | | | | | | | | | | My recent patch to add support for ISA 2.07 vector pack/unpack instructions didn't properly check for availability of the vpkudum instruction when recognizing it as a special vector shuffle case. This causes us to leave the vector shuffle in place (rather than converting it to a vector permute) so that it can be recognized later as a vpkudum, but that pattern is invalid for processors prior to POWER8. Thus LLVM crashes with an "unable to select" message. We observed this since one of our buildbots is configured to generate code for a POWER7. This patch fixes the problem by checking for availability of the vpkudum instruction during custom lowering of vector shuffles. I've added a test case variant for the vpkudum pattern when the instruction isn't available. llvm-svn: 237952
* [PPC/LoopUnrollRuntime] Don't avoid high-cost trip count computation on the ↵Hal Finkel2015-05-211-0/+4
| | | | | | | | | | | | | PPC/A2 On X86 (and similar OOO cores) unrolling is very limited, and even if the runtime unrolling is otherwise profitable, the expense of a division to compute the trip count could greatly outweigh the benefits. On the A2, we unroll a lot, and the benefits of unrolling are more significant (seeing a 5x or 6x speedup is not uncommon), so we're more able to tolerate the expense, on average, of a division to compute the trip count. llvm-svn: 237947
* Add support for VSX scalar single-precision arithmetic in the PPC targetNemanja Ivanovic2015-05-211-46/+82
| | | | | | | | | | | | | | | | | http://reviews.llvm.org/D9891 Following up on the VSX single precision loads and stores added earlier, this adds support for elementary arithmetic operations on single precision values in VSX registers. These instructions utilize the new VSSRC register class. Instructions added: xsaddsp xsdivsp xsmulsp xsresp xsrsqrtesp xssqrtsp xssubsp llvm-svn: 237937
* Move alignment from MCSectionData to MCSection.Rafael Espindola2015-05-2130-125/+117
| | | | | | | | | | | | | | | | | | | | | | | | This starts merging MCSection and MCSectionData. There are a few issues with the current split between MCSection and MCSectionData. * It optimizes the the not as important case. We want the production of .o files to be really fast, but the split puts the information used for .o emission in a separate data structure. * The ELF/COFF/MachO hierarchy is not represented in MCSectionData, leading to some ad-hoc ways to represent the various flags. * It makes it harder to remember where each item is. The attached patch starts merging the two by moving the alignment from MCSectionData to MCSection. Most of the patch is actually just dropping 'const', since MCSectionData is mutable, but MCSection was not. llvm-svn: 237936
* AVX-512: Enabled SSE intrinsics on AVX-512.Elena Demikhovsky2015-05-212-14/+33
| | | | | | | | | Predicate UseAVX depricates pattern selection on AVX-512. This predicate is necessary for DAG selection to select EVEX form. But mapping SSE intrinsics to AVX-512 instructions is not ready yet. So I replaced UseAVX with HasAVX for intrinsics patterns. llvm-svn: 237903
* Fixed unused variable warning in non-assert builds from rL237885Simon Pilgrim2015-05-211-2/+1
| | | | llvm-svn: 237889
* [X86][SSE] Improve support for 128-bit vector sign extensionSimon Pilgrim2015-05-211-6/+115
| | | | | | | | | | This patch improves support for sign extension of the lower lanes of vectors of integers by making use of the SSE41 pmovsx* sign extension instructions where possible, and optimizing the sign extension by shifts on pre-SSE41 targets (avoiding the use of i64 arithmetic shifts which require scalarization). It converts SIGN_EXTEND nodes to SIGN_EXTEND_VECTOR_INREG where necessary, that more closely matches the pmovsx* instruction than the default approach of using SIGN_EXTEND_INREG which splits the operation (into an ANY_EXTEND lowered to a shuffle followed by shifts) making instruction matching difficult during lowering. Necessary support for SIGN_EXTEND_VECTOR_INREG has been added to the DAGCombiner. Differential Revision: http://reviews.llvm.org/D9848 llvm-svn: 237885
* [WinEH] Store pointers to the LSDA in the exception registration objectReid Kleckner2015-05-202-13/+88
| | | | | | | We aren't yet emitting the LSDA yet, so this will still fail to assemble. llvm-svn: 237852
* Revert r237828 "[X86] Remove unused node after morphing it from shr to and."Hans Wennborg2015-05-201-1/+0
| | | | | | This caused assertions during DAG combine: PR23601. llvm-svn: 237843
* [Target/ARM] Only enable OptimizeBarrierPass at -O1 and above.Davide Italiano2015-05-201-1/+4
| | | | | | | | | | Ideally this is going to be and LLVM IR pass (shared, among others with AArch64), but for the time being just enable it if consumers ask us for optimization and not unconditionally. Discussed with Tim Northover on IRC. llvm-svn: 237837
* MC: Remove most remaining uses of MCSymbolData::getSymbol(), NFCDuncan P. N. Exon Smith2015-05-201-7/+5
| | | | | | | Remove most remaining calls to `MCSymbolData::getSymbol()`, instead using the already available `MCSymbol` directly. llvm-svn: 237829
* [X86] Remove unused node after morphing it from shr to and.Benjamin Kramer2015-05-201-0/+1
| | | | | | | | | In some cases it won't get cleaned up properly leading to crashes downstream. PR23353. Based on a patch by Davide Italiano. llvm-svn: 237828
* ARM: Fix comment and make it slightly more readableMatthias Braun2015-05-201-7/+7
| | | | llvm-svn: 237820
* Change Function::getIntrinsicID() to return an Intrinsic::ID. NFC.Pete Cooper2015-05-201-2/+2
| | | | | | | | Now that Intrinsic::ID is a typed enum, we can forward declare it and so return it from this method. This updates all users which were either using an unsigned to store it, or had a now unnecessary cast. llvm-svn: 237810
* MC: Update MCAssembler to use MCSymbol, NFCDuncan P. N. Exon Smith2015-05-202-6/+6
| | | | | | Use `MCSymbol` over `MCSymbolData` where both are needed. llvm-svn: 237803
* MC: Use MCSymbol in MachObjectWriter, NFCDuncan P. N. Exon Smith2015-05-203-43/+38
| | | | | | | Replace uses of `MCSymbolData` with `MCSymbol` where both are needed, so we can remove the backpointer. llvm-svn: 237799
* AVX-512: fixed algorithm of building vectors of i1 elementsElena Demikhovsky2015-05-203-65/+134
| | | | | | | | fixed extract-insert i1 element, load i1, zextload i1 should be with "and $1, %reg" to prevent loading garbage. added a bunch of new tests. llvm-svn: 237793
* Revert r237789 - [mips] The naming convention for private labels is ABI ↵Daniel Sanders2015-05-205-23/+2
| | | | | | | | | dependant. It works, but I've noticed that I missed several callers of createMCAsmInfo() and many don't have a TargetMachine to provide. llvm-svn: 237792
* [mips] The naming convention for private labels is ABI dependant.Daniel Sanders2015-05-205-2/+23
| | | | | | | | | | | | | | | | | Summary: For N32/N64, private labels begin with '.L' but for O32 they begin with '$'. MCAsmInfo now has an initializer function which can be used to provide information from the TargetMachine to control the assembly syntax. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: jfb, sandeep, llvm-commits, rafael Differential Revision: http://reviews.llvm.org/D9821 llvm-svn: 237789
* [mips] [IAS] Factor out .set nomacro warning. NFC.Toma Tabacu2015-05-201-8/+11
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9772 llvm-svn: 237780
* [X86] Implement the local-exec TLS model for Windows targetsDavid Majnemer2015-05-201-14/+19
| | | | | | | We know that _tls_index is zero for local-exec TLS variables because they are always defined in the executable. llvm-svn: 237772
* [bpf] fix buildAlexei Starovoitov2015-05-201-1/+1
| | | | llvm-svn: 237751
* MC: Take MCSymbol in MachObjectWriter::getSymbolAddress(), NFCDuncan P. N. Exon Smith2015-05-204-30/+26
| | | | | | | Pass through an `MCSymbol` instead of an `MCSymbolData` so we can get rid of the back pointer. llvm-svn: 237750
* MC: Use MCSymbol in MCAsmLayout::getSymbolOffset(), NFCDuncan P. N. Exon Smith2015-05-194-10/+10
| | | | | | | Continue to canonicalize on MCSymbol instead of MCSymbolData when both are needed. llvm-svn: 237749
* MachineInstr: Remove unused parameter.Matthias Braun2015-05-193-4/+3
| | | | llvm-svn: 237726
* Remove unnecessary cast. NFCPete Cooper2015-05-191-1/+1
| | | | llvm-svn: 237722
* [mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructionsZoran Jovanovic2015-05-192-7/+22
| | | | | | Differential Revision: http://reviews.llvm.org/D8800 llvm-svn: 237697
* [mips][microMIPSr6] Implement AND and ANDI instructionsZoran Jovanovic2015-05-192-3/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D8772 llvm-svn: 237696
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