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* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-0740-166/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. For MachineOperand::print, keep a simple version that can be easily called from `dump()`, and a more complex one which will be called from both the MIRPrinter and MachineInstr::print. Add extra checks inside MachineOperand for detached operands (operands with getParent() == nullptr). https://reviews.llvm.org/D40836 * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+)<def> ([^ ]+)/kill: \1 def \2 \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: def ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: def \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/<def>//g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<kill>/killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use,kill>/implicit killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<def[ ]*,[ ]*dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def[ ]*,[ ]*dead>/implicit-def dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def>/implicit-def \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use>/implicit \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<internal>/internal \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<undef>/undef \1/g' llvm-svn: 320022
* [RISCV] MC layer support for the standard RV32F instruction set extensionAlex Bradbury2017-12-0711-13/+397
| | | | | | | | | | | | | The most interesting part of this patch is probably the handling of rounding mode arguments. Sadly, the RISC-V assembler handles floating point rounding modes as a special "argument" when it would be more consistent to handle them like the atomics, opcode suffixes. This patch supports parsing this optional parameter, using InstAlias to allow parsing these floating point instructions when no rounding mode is specified. Differential Revision: https://reviews.llvm.org/D39893 llvm-svn: 320020
* [AVR] Override ParseDirectiveLeslie Zhai2017-12-0711-22/+275
| | | | | | | | | | Reviewers: dylanmckay, kparzysz Reviewed By: dylanmckay Differential Revision: https://reviews.llvm.org/D38029 llvm-svn: 320009
* [WebAssembly] Don't try to emit size information for unsized typesDan Gohman2017-12-071-5/+7
| | | | | | | | | | Patch by John Sully! Fixes PR35164. Differential Revision: https://reviews.llvm.org/D39519 llvm-svn: 319991
* [AArch64] Add patterns to replace fsub fmul with fma fneg.Florian Hahn2017-12-061-3/+102
| | | | | | | | | | | | | | | | | | | Summary: This patch adds MachineCombiner patterns for transforming (fsub (fmul x y) z) into (fma x y (fneg z)). This has a lower latency on micro architectures where fneg is cheap. Patch based on work by George Steed. Reviewers: rengolin, joelkevinjones, joel_k_jones, evandro, efriedma Reviewed By: evandro Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D40306 llvm-svn: 319980
* [Hexagon] Recognize vdealb, vdealh, vshuffb and vshuffh specificallyKrzysztof Parzyszek2017-12-061-4/+37
| | | | llvm-svn: 319978
* [Hexagon] Handle perfect shuffles on single vectorsKrzysztof Parzyszek2017-12-061-6/+19
| | | | llvm-svn: 319965
* [WebAssembly] Remove WASM_STACK_POINTER.Dan Gohman2017-12-063-28/+0
| | | | | | | WASM_STACK_POINTER and the .stack_pointer directive are no longer needed now that the stack pointer global is an import. llvm-svn: 319956
* [ModRefInfo] Do not use ModRefInfo result in if conditions as this makesAlina Sbirlea2017-12-061-1/+2
| | | | | | | assumptions about the values in the enum. Replace with wrapper returning bool [NFC]. llvm-svn: 319949
* [X86][AVX512] Tag mask reg op instruction scheduler classesSimon Pilgrim2017-12-062-57/+70
| | | | llvm-svn: 319945
* [Hexagon] Suppress more warnings on unused variables defined for asserts.Tim Shen2017-12-061-0/+1
| | | | llvm-svn: 319944
* [Hexagon] Suppress warnings on unused variables defind for asserts.Tim Shen2017-12-061-0/+2
| | | | llvm-svn: 319940
* [Target] dumpr() is defined only in debug builds.Davide Italiano2017-12-061-0/+2
| | | | | | This fixes the clang build on macOS. llvm-svn: 319923
* [X86][AVX512] Tag scalar insert/extract instruction scheduler classesSimon Pilgrim2017-12-061-17/+22
| | | | | | Classes don't look great but match what we're doing on SSE/AVX llvm-svn: 319920
* [X86] Simplify the TTI code for getInterleavedMemoryOpCost around for ↵Craig Topper2017-12-061-9/+4
| | | | | | | | | | AVX512BW. NFCI Previously the lambda for AVX512 passed out a flag that indicated whether AVX512BW was required and that was checked against the AVX512BW subtarget flag outside. This patch changes the interface to pass the AVX512BW subtarget bit in and return its value if we detect 16 or 8 bit types. llvm-svn: 319919
* [X86][AVX2] Tag MASKMOV instruction scheduler classesSimon Pilgrim2017-12-061-11/+16
| | | | llvm-svn: 319915
* [X86][AVX512] Tag aligned/unaligned move instruction scheduler classesSimon Pilgrim2017-12-062-68/+85
| | | | llvm-svn: 319913
* [NVPTX,CUDA] Added llvm.nvvm.fns intrinsic and matching __nvvm_fns builtin ↵Artem Belevich2017-12-061-0/+27
| | | | | | | | in clang. Differential Revision: https://reviews.llvm.org/D40872 llvm-svn: 319909
* [SystemZ] Add IntrWriteMem flag to int_s390_tabort intrinsicJonas Paulsson2017-12-061-2/+1
| | | | | | | | | Tabort (transaction abort) does not load from memory. mayLoad flag removed from corresponding TABORT machine instruction. Review: Ulrich Weigand llvm-svn: 319905
* [Hexagon] Generate HVX code for vector construction and accessKrzysztof Parzyszek2017-12-068-248/+2468
| | | | | | | | | | Support for: - build vector, - extract vector element, subvector, - insert vector element, subvector, - shuffle. llvm-svn: 319901
* [X86][AVX512] Tag BROADCAST instruction scheduler classesSimon Pilgrim2017-12-061-39/+61
| | | | llvm-svn: 319900
* [ARM][AArch64][DAG] Reenable post-legalize store mergeNirav Dave2017-12-062-6/+0
| | | | | | | | | | | | | | | | | | | | Reenable post-legalize stores with constant merging computation and corresponding test case. * Properly truncate store merge constants * Disable merging of truncated stores floating points * Ensure merges of constant stores into a single vector are constructed from legal elements. Reviewers: eastig, efriedma Reviewed By: eastig Subscribers: spatel, rengolin, aemerson, javed.absar, kristof.beyls, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40701 llvm-svn: 319899
* [SystemZ] Bugfix in expandRxSBG()Jonas Paulsson2017-12-061-2/+9
| | | | | | | | | | | | Csmith discovered a program that caused wrong code generation with -O0: When handling a SIGN_EXTEND in expandRxSBG(), RxSBG.BitSize may be less than the Input width (if a truncate was previously traversed), so maskMatters() should be called with a masked based on the width of the sign extend result instead. Review: Ulrich Weigand llvm-svn: 319892
* [X86] Avoid unused variable warning in Release builds. NFCI.Benjamin Kramer2017-12-061-3/+3
| | | | llvm-svn: 319891
* [X86][AVX512] Drop default NoItinerary arguments that aren't neededSimon Pilgrim2017-12-061-6/+6
| | | | | | Requires reordering of AVX512_maskable_common arguments, but helps track what is still missing itinerary tags llvm-svn: 319890
* [mips] Fix definition of 'bc' instructionSimon Dardis2017-12-061-3/+1
| | | | llvm-svn: 319888
* [X86][AVX512] Tag Mask<->Vector instructions scheduler classesSimon Pilgrim2017-12-061-2/+4
| | | | llvm-svn: 319887
* [X86][AVX512] Cleanup scalar move scheduler classesSimon Pilgrim2017-12-061-31/+31
| | | | llvm-svn: 319884
* [X86] Split 512-bit vector extends from types other than vXi1 out of ↵Craig Topper2017-12-061-42/+36
| | | | | | | | LowerZERO_EXTEND_AVX512/LowerSIGN_EXTEND_AVX512. NFCI Most of the code in these routines is for handling extends from vXi1 types. The 512-bit handling for other extends is very much like the AVX2 code. So make the special routines just do vXi1 types and move the other 512-bit handling to the place that handles AVX2. llvm-svn: 319878
* [WebAssembly] Only emit stack pointer delcaration in BinFormatWasm assemblyDerek Schuff2017-12-061-2/+4
| | | | llvm-svn: 319870
* [X86] Update to getSetCCResultType to be more robust to EVT types.Craig Topper2017-12-061-28/+17
| | | | | | Attempt to determine what the type will be legalized to and then analyze that to see if we will be able to use a vXi1 compare. llvm-svn: 319861
* [AArch64] Do not abort if overflow check does not use EQ or NE.Joel Galenson2017-12-051-3/+2
| | | | | | | | | | As suggested by Eli Friedman, instead of aborting if an overflow check uses something other than SETEQ or SETNE, simply do not apply the optimization. Differential Revision: https://reviews.llvm.org/D39147 llvm-svn: 319837
* [X86][AVX512] Tag BLENDM instruction scheduler classesSimon Pilgrim2017-12-051-28/+45
| | | | llvm-svn: 319833
* [X86][AVX512] Tag GATHER/SCATTER instruction scheduler classesSimon Pilgrim2017-12-052-7/+11
| | | | | NOTE: At the moment these use the WriteLoad/WriteStore classes, which severely underestimates the costs. This needs to be reviewed. llvm-svn: 319829
* AMDGPU: Fix SDWA crash on inline asmMatt Arsenault2017-12-051-1/+2
| | | | | | | | This was only searching for explicit defs, and asserting for any implicit or variadic instruction defs, like inline asm. llvm-svn: 319826
* Re-commit r319490 "XOR the frame pointer with the stack cookie when ↵Hans Wennborg2017-12-054-0/+41
| | | | | | | | | | | | | | | | | | protecting the stack" The patch originally broke Chromium (crbug.com/791714) due to its failing to specify that the new pseudo instructions clobber EFLAGS. This commit fixes that. > Summary: This strengthens the guard and matches MSVC. > > Reviewers: hans, etienneb > > Subscribers: hiraditya, JDevlieghere, vlad.tsyrklevich, llvm-commits > > Differential Revision: https://reviews.llvm.org/D40622 llvm-svn: 319824
* [X86][AVX512] Tag VPSLLDQ/VPSRLDQ instruction scheduler classesSimon Pilgrim2017-12-051-9/+20
| | | | llvm-svn: 319822
* Modify ModRefInfo values using static inline method abstractions [NFC].Alina Sbirlea2017-12-051-1/+2
| | | | | | | | | | | | | | | | | Summary: The aim is to make ModRefInfo checks and changes more intuitive and less error prone using inline methods that abstract the bit operations. Ideally ModRefInfo would become an enum class, but that change will require a wider set of changes into FunctionModRefBehavior. Reviewers: sanjoy, george.burgess.iv, dberlin, hfinkel Subscribers: nlopes, llvm-commits Differential Revision: https://reviews.llvm.org/D40749 llvm-svn: 319821
* [SystemZ] Validate shifted compare value in adjustForTestUnderMaskUlrich Weigand2017-12-051-0/+2
| | | | | | | | | | | When folding a shift into a test-under-mask comparison, make sure that there is no loss of precision when creating the shifted comparison value. This usually never happens, except for certain always-true comparisons in unoptimized code. Fixes PR35529. llvm-svn: 319818
* [X86][AVX512] Tag VPTRUNC/VPMOVSX/VPMOVZX instruction scheduler classesSimon Pilgrim2017-12-051-90/+106
| | | | llvm-svn: 319815
* AMDGPU: Fix infinite loop with dbg_valueMatt Arsenault2017-12-051-1/+4
| | | | | | | | | Surprisingly SIOptimizeExecMaskingPreRA can infinite loop in some case with DBG_VALUE. Most tests using dbg_value are run at -O0, so don't run this pass. This seems to only happen when the value argument is undef. llvm-svn: 319808
* [X86][X87] Tag FCMOV instruction scheduler classesSimon Pilgrim2017-12-054-16/+22
| | | | llvm-svn: 319804
* [WebAssembly] Implement WASM_STACK_POINTER.Dan Gohman2017-12-053-9/+14
| | | | | | | Use the .stack_pointer directive to implement WASM_STACK_POINTER for specifying a global variable to be the stack pointer. llvm-svn: 319797
* [WebAssembly] Don't emit .import_global for the wasm target.Dan Gohman2017-12-051-1/+2
| | | | | | | .import_global is used by the ELF-based target and not needed by the wasm target. llvm-svn: 319796
* [X86][AVX512] Tag VNNIW instruction scheduler classesSimon Pilgrim2017-12-051-15/+18
| | | | llvm-svn: 319784
* [X86][AVX512] Drop some default NoItinerary arguments that aren't needed any ↵Simon Pilgrim2017-12-051-9/+10
| | | | | | more llvm-svn: 319782
* [x86][AVX512] Lowering kunpack intrinsics to LLVM IRJina Nahias2017-12-052-3/+47
| | | | | | | | | This patch, together with a matching clang patch (https://reviews.llvm.org/D39719), implements the lowering of X86 kunpack intrinsics to IR. Differential Revision: https://reviews.llvm.org/D39720 Change-Id: I4088d9428478f9457f6afddc90bd3d66b3daf0a1 llvm-svn: 319778
* [X86][AVX512] Tag VPMADD52/VPSADBW instruction scheduler classesSimon Pilgrim2017-12-051-22/+25
| | | | llvm-svn: 319772
* [X86][AVX512] Add missing scalar CMPSS/CMPSD logic scheduler classesSimon Pilgrim2017-12-051-16/+21
| | | | llvm-svn: 319770
* [X86][AVX512] Cleanup bit logic scheduler classesSimon Pilgrim2017-12-051-21/+24
| | | | llvm-svn: 319767
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