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* expand PICLDR MC lowering to handle other PICLDR and PICSTR versions.Jim Grosbach2010-09-171-11/+31
| | | | llvm-svn: 114183
* AlphaSchedule.td: 7bit-ize.NAKAMURA Takumi2010-09-171-1/+1
| | | | llvm-svn: 114173
* fix rdar://8438816 - unrecognized 'fildq' instructionChris Lattner2010-09-161-1/+2
| | | | llvm-svn: 114116
* MC-ization of the PICLDR pseudo. Next up, adding the other variantsJim Grosbach2010-09-162-1/+33
| | | | | | (PICLDRB, et. al.) and PICSTR* llvm-svn: 114098
* Make sure to promote single precision floats to double before extracting themJim Grosbach2010-09-161-2/+4
| | | | | | from the APFloat. llvm-svn: 114096
* Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.Kalle Raiskila2010-09-163-238/+177
| | | | | | | | | | | | | This cleans up after the mess r108567 left in the CellSPU backend. ORCvt-instruction were used to reinterpret registers, and the ORs were then removed by isMoveInstr(). This patch now removes 350 instrucions of format: or $3, $3, $3 (from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is checked for. Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain. llvm-svn: 114074
* Remove support for "dregpair" operand modifier, now that it is no longer beingBob Wilson2010-09-162-36/+2
| | | | | | used for anything. llvm-svn: 114067
* When expanding ARM pseudo registers, copy the existing predicate operandsBob Wilson2010-09-161-9/+29
| | | | | | instead of using default predicates on the expanded instructions. llvm-svn: 114066
* store MC FP immediates as a double instead of as an APFloat, thus avoiding anJim Grosbach2010-09-163-4/+8
| | | | | | unnecessary dtor for MCOperand. llvm-svn: 114064
* Add missing break.Bob Wilson2010-09-161-0/+1
| | | | llvm-svn: 114048
* Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded afterBob Wilson2010-09-163-15/+70
| | | | | | | register allocation to VLDMD and VSTMD respectively. This avoids using the dregpair operand modifier. llvm-svn: 114047
* Add support for the 'lane' modifier on vdup operandsJim Grosbach2010-09-151-7/+25
| | | | llvm-svn: 114030
* Remember VLDMQ.Jakob Stoklund Olesen2010-09-151-0/+9
| | | | llvm-svn: 114026
* Add missing break.Jakob Stoklund Olesen2010-09-151-0/+1
| | | | llvm-svn: 114025
* Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to registerJim Grosbach2010-09-151-8/+7
| | | | | | | moves. Previously, the immediate was printed as the encoded integer value, which is incorrect. llvm-svn: 114021
* move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helperJim Grosbach2010-09-157-87/+80
| | | | | | | | | functions in ARMBaseInfo.h so it can be used in the MC library as well. For anything bigger than this, we may want a means to have a small support library for shared helper functions like this. Cross that bridge when we come to it. llvm-svn: 114016
* simplify getRegisterNumbering(). Remove the unused isSPVFP argument andJim Grosbach2010-09-152-90/+37
| | | | | | merge the common cases. llvm-svn: 114013
* Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. CheckJim Grosbach2010-09-151-6/+6
| | | | | | if the register is a member of the SPR register class directly instead. llvm-svn: 114012
* Reduce dependencies in the ARM MC instruction printer.Jim Grosbach2010-09-151-1/+1
| | | | llvm-svn: 114009
* Fix spelling typo.Jim Grosbach2010-09-151-1/+1
| | | | llvm-svn: 114008
* Factor out basic enums and hleper functions from ARM.h for cleaner sharingJim Grosbach2010-09-152-101/+129
| | | | | | between the compiler back end and the MC libraries. llvm-svn: 114007
* Add support for floating point immediates to MC instruction printing. ARMJim Grosbach2010-09-152-2/+6
| | | | | | | | | | | VFP instructions use it for loading some constants, so implement that handling. Not thrilled with adding a member to MCOperand, but not sure there's much of a better option that's not pretty fragile (like putting a double in the union instead and just assuming that's good enough). Suggestions welcome... llvm-svn: 113996
* Recognize VST1q64Pseudo and VSTMQ as stack slot stores.Jakob Stoklund Olesen2010-09-151-0/+22
| | | | | | | | | Recognize VLD1q64Pseudo as a stack slot load. Reject these if they are loading or storing a subregister. The API (and VirtRegRewriter) doesn't know how to deal with that. llvm-svn: 113985
* Reapply Gabor's 113839, 113840, and 113876 with a fix for a problemBob Wilson2010-09-151-0/+17
| | | | | | | | encountered while building llvm-gcc for arm. This is probably the same issue that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator, not a plain MachineInstr. llvm-svn: 113983
* the darwin9-powerpc buildbot keeps consistently crashing,Gabor Greif2010-09-151-16/+0
| | | | | | | | | | backing out following to get it back to green, so I can investigate in peace: svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm-svn: 113980
* Move ARM is{LoadFrom,StoreTo}StackSlot closer to their siblings so they won't beJakob Stoklund Olesen2010-09-151-78/+64
| | | | | | | | | | forgotten in the future. Coalesce identical cases in switch. No functional changes intended. llvm-svn: 113979
* Spelling fix.Bob Wilson2010-09-152-2/+2
| | | | llvm-svn: 113978
* lcall and ljmp always default to lcalll and ljmpl. This finallyChris Lattner2010-09-151-10/+8
| | | | | | wraps up r8418316 llvm-svn: 113949
* apparently jmpl $1,$2 is an alias for ljmpl, similiarlyChris Lattner2010-09-151-0/+21
| | | | | | for call. Add this. llvm-svn: 113948
* Disambiguate lcall/ljmp to the 32-bit version. This happensChris Lattner2010-09-151-0/+10
| | | | | | even in 64-bit mode apparently. llvm-svn: 113945
* fix the encoding of sldt GR16 to have the 0x66 prefix, andChris Lattner2010-09-151-1/+3
| | | | | | | add sldt GR32, which isn't documented in the intel manual but which gas accepts. Part of rdar://8418316 llvm-svn: 113938
* implement aliases for shld/shrd, part of rdar://8418316Chris Lattner2010-09-151-0/+9
| | | | llvm-svn: 113937
* fix rdar://8431880 - rcl/rcr with no shift amount not recognizedChris Lattner2010-09-151-1/+9
| | | | llvm-svn: 113936
* add various broken forms of fnstsw. I didn't add the %raxChris Lattner2010-09-151-0/+19
| | | | | | | version because it adds a prefix and makes even less sense than the other broken forms. This wraps up rdar://8431422 llvm-svn: 113932
* add some aliases for f[u]comi, part of rdar://8431422Chris Lattner2010-09-151-7/+9
| | | | llvm-svn: 113930
* add a bunch of aliases for fp operations with no operand,Chris Lattner2010-09-151-5/+22
| | | | | | rdar://8431422 llvm-svn: 113929
* Diagnose invalid instructions like "incl" with "too few operands for ↵Chris Lattner2010-09-151-2/+4
| | | | | | | | | instruction" instead of crashing. This fixes: rdar://8431815 - crash when invalid operand is one that isn't present llvm-svn: 113921
* Use VLD1/VST1 pseudo instructions for loadRegFromStackSlot andBob Wilson2010-09-152-33/+9
| | | | | | storeRegToStackSlot. llvm-svn: 113918
* trailing whitespaceJim Grosbach2010-09-151-25/+25
| | | | llvm-svn: 113915
* Add x86MMX a few more places.Dale Johannesen2010-09-151-0/+1
| | | | llvm-svn: 113914
* Reapply r113875 with additional cleanups.Jim Grosbach2010-09-143-116/+33
| | | | | | | | | | | | | | | "The register specified for a dregpair is the corresponding Q register, so to get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01])." Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use the dregpair modifier for the 2xdreg versions. Explicitly specifying the two registers as operands is more correct and more consistent with the other instruction patterns. This enables further cleanup of special case code in the disassembler as a nice side-effect. llvm-svn: 113903
* add a terrible hack to allow out with dx is parens, a gas bug.Chris Lattner2010-09-141-0/+14
| | | | | | This fixes PR8114 llvm-svn: 113894
* Emit libcalls for SDIV, this requires some call infrastructureEric Christopher2010-09-141-0/+154
| | | | | | that needs to be shared a bit more widely around. llvm-svn: 113886
* revert 113875 momentarilly. Need to fix the MC disassembler to handle theJim Grosbach2010-09-141-23/+77
| | | | | | change. llvm-svn: 113878
* trailing whitespace cleanupJim Grosbach2010-09-141-23/+23
| | | | llvm-svn: 113877
* an attempt to salvage the darwin9-powerpc buildbot, which could be ↵Gabor Greif2010-09-141-1/+2
| | | | | | miscompiling this line llvm-svn: 113876
* The register specified for a dregpair is the corresponding Q register, so toJim Grosbach2010-09-141-77/+23
| | | | | | | | get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01]). llvm-svn: 113875
* set isCompare for another three Thumb1 instructionsGabor Greif2010-09-141-2/+2
| | | | llvm-svn: 113867
* Add predicate and 's' bit operands to PICADD instruction lowering.Jim Grosbach2010-09-141-0/+5
| | | | llvm-svn: 113860
* Avoid warnings.Bob Wilson2010-09-141-2/+3
| | | | llvm-svn: 113857
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