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* [AArch64] Use a static function and other minor cleanup for readability. NFC.Chad Rosier2015-08-061-11/+12
| | | | llvm-svn: 244233
* [AArch64] Improve the readability of the ld/st optimization pass. NFC.Chad Rosier2015-08-061-37/+48
| | | | llvm-svn: 244222
* [SPARC] Don't compare arch name as a string, use the enum instead.Douglas Katzman2015-08-061-1/+1
| | | | | | Fixes PR22695 llvm-svn: 244221
* Removing tailing whitespacesMichael Liao2015-08-061-62/+62
| | | | llvm-svn: 244203
* [X86] Improve EmitLoweredSelect for contiguous CMOV pseudo instructions.Michael Kuperstein2015-08-061-33/+159
| | | | | | | | | | | | This change improves EmitLoweredSelect() so that multiple contiguous CMOV pseudo instructions with the same (or exactly opposite) conditions get lowered using a single new basic-block. This eliminates unnecessary extra basic-blocks (and CFG merge points) when contiguous CMOVs are being lowered. Patch by: kevin.b.smith@intel.com Differential Revision: http://reviews.llvm.org/D11428 llvm-svn: 244202
* MIR Serialization: Initial serialization of the machine operand target flags.Alex Lorenz2015-08-062-0/+41
| | | | | | | | | | | | This commit implements the initial serialization of the machine operand target flags. It extends the 'TargetInstrInfo' class to add two new methods that help to provide text based serialization for the target flags. This commit can serialize only the X86 target flags, and the target flags for the other targets will be serialized in the follow-up commits. Reviewers: Duncan P. N. Exon Smith llvm-svn: 244185
* x86: NFC remove needless InstrCompiler castJF Bastien2015-08-051-15/+15
| | | | | | | | | | Summary: The casts from String to PatFrag weren't needed if we instead provided an SDNode. This fix was suggested by @pete in D11382. Subscribers: pete, llvm-commits Differential Revision: http://reviews.llvm.org/D11788 llvm-svn: 244167
* [NVPTX] Use LDG for pointer induction variables.Bjarke Hammersholt Roune2015-08-051-10/+29
| | | | | | | | More specifically, make NVPTXISelDAGToDAG able to emit cached loads (LDG) for pointer induction variables. Also fix latent bug where LDG was not restricted to kernel functions. I believe that this could not be triggered so far since we do not currently infer that a pointer is global outside a kernel function, and only loads of global pointers are considered for cached loads. llvm-svn: 244166
* -Wdeprecated: Remove some dead code that was relying on a questionable ↵David Blaikie2015-08-052-49/+0
| | | | | | (rule-of-3-violating) copy ctor in MCInstPrinter llvm-svn: 244133
* [Hexagon] Edit a comment. NFCKrzysztof Parzyszek2015-08-051-7/+1
| | | | llvm-svn: 244130
* x86 atomic: optimize a.store(reg op a.load(acquire), release)JF Bastien2015-08-054-19/+114
| | | | | | | | | | | | Summary: PR24191 finds that the expected memory-register operations aren't generated when relaxed { load ; modify ; store } is used. This is similar to PR17281 which was addressed in D4796, but only for memory-immediate operations (and for memory orderings up to acquire and release). This patch also handles some floating-point operations. Reviewers: reames, kcc, dvyukov, nadav, morisset, chandlerc, t.p.northover, pete Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11382 llvm-svn: 244128
* Revert "Fix MO's analyzePhysReg, it was confusing sub- and super-registers. ↵JF Bastien2015-08-051-48/+26
| | | | | | | | Problem pointed out by Michael Hordijk." I mistakenly committed the patch for D6629, and was trying to commit another. Reverting until it gets proper signoff. llvm-svn: 244121
* Fix MO's analyzePhysReg, it was confusing sub- and super-registers. Problem ↵JF Bastien2015-08-051-26/+48
| | | | | | pointed out by Michael Hordijk. llvm-svn: 244120
* [Hexagon] Implement TargetTransformInfo for HexagonKrzysztof Parzyszek2015-08-055-7/+155
| | | | | Author: Brendon Cahoon <bcahoon@codeaurora.org> llvm-svn: 244089
* [TTI] Make the cost APIs in TargetTransformInfo consistently use 'int'Chandler Carruth2015-08-0512-228/+203
| | | | | | | | | | | | | | | | | | | | | | | | | | rather than 'unsigned' for their costs. For something like costs in particular there is a natural "negative" value, that of savings or saved cost. As a consequence, there is a lot of code that subtracts or creates negative values based on cost, all of which is prone to awkwardness or bugs when dealing with an unsigned type. Similarly, we *never* want these values to wrap, as that would cause Very Bad code generation (likely percieved as an infinite loop as we try to emit over 2^32 instructions or some such insanity). All around 'int' seems a much better fit for these basic metrics. I've added asserts to ensure that at least the TTI interface never returns negative numbers here. If we ever have a use case for negative numbers, we can remove this, but this way a bug where someone used '-1' to produce a 'very large' cost will be caught by the assert. This passes all tests, and is also UBSan clean. No functional change intended. Differential Revision: http://reviews.llvm.org/D11741 llvm-svn: 244080
* Move BB succ_iterator to be inside TerminatorInst. NFC.Pete Cooper2015-08-051-2/+2
| | | | | | | | | | | | | | | | | | | | | To get the successors of a BB we currently do successors(BB) which ultimately walks the successors of the BB's terminator. This moves the iterator to TerminatorInst as thats what we're actually using to do the iteration, and adds a member function to TerminatorInst to allow us to iterate directly over successors given an instruction. For example, we can now do for (auto *Succ : BI->successors()) instead of for (unsigned i = 0, e = BI->getNumSuccessors(); i != e; ++i) Reviewed by Tobias Grosser. llvm-svn: 244074
* [AArch64] Register AArch64DeadRegisterDefinition pass with LLVM pass manager.Chad Rosier2015-08-051-2/+14
| | | | llvm-svn: 244067
* [Sparc] Fix disassembly of popc instruction.James Y Knight2015-08-051-2/+2
| | | | | | | | And add tests. Patch by David Wiberg! llvm-svn: 244064
* AMDGPU/SI: Remove EXECRegMatt Arsenault2015-08-055-21/+9
| | | | | | For the same reasons as the other physical registers. llvm-svn: 244062
* AMDGPU: Remove SCCReg.Matt Arsenault2015-08-055-36/+22
| | | | | | | These should be handled as a physical register rather than a virtual register class with one member. llvm-svn: 244061
* [AArch64] Register (existing) AArch64BranchRelaxation pass with LLVM pass ↵Chad Rosier2015-08-051-2/+13
| | | | | | | | | manager. Summary: Among other things, this allows -print-after-all/-print-before-all to dump IR around this pass. llvm-svn: 244060
* [AArch64] Make the naming of the Address Type Promotion pass consistent.Chad Rosier2015-08-051-3/+5
| | | | llvm-svn: 244057
* [AArch64] Register (existing) AArch64AdvSIMDScalar pass with LLVM pass manager.Chad Rosier2015-08-051-2/+13
| | | | | | | | | Summary: Among other things, this allows -print-after-all/-print-before-all to dump IR around this pass. IIRC, this pass is off by default, but it's still helpful when debugging. llvm-svn: 244056
* Make this less error prone by using a #define. NFC.Chad Rosier2015-08-051-5/+5
| | | | llvm-svn: 244048
* [AArch64] Register (existing) AArch64ExpandPseudo pass with LLVM pass manager.Chad Rosier2015-08-051-2/+13
| | | | | | | Summary: Among other things, this allows -print-after-all/-print-before-all to dump IR around this pass. llvm-svn: 244046
* [AArch64] Register (existing) AArch64LoadStoreOpt pass with LLVM pass manager.Chad Rosier2015-08-051-2/+13
| | | | | | | | | Summary: Among other things, this allows -print-after-all/-print-before-all to dump IR around this pass. This is the AArch64 version of r243052. llvm-svn: 244041
* Update comment. NFC.Chad Rosier2015-08-051-2/+2
| | | | llvm-svn: 244038
* ARMISelDAGToDAG.cpp had this self-contradictory code:Artyom Skrobov2015-08-051-5/+5
| | | | | | | | | | | | | | | | | | return StringSwitch<int>(Flags) .Case("g", 0x1) .Case("nzcvq", 0x2) .Case("nzcvqg", 0x3) .Default(-1); ... // The _g and _nzcvqg versions are only valid if the DSP extension is // available. if (!Subtarget->hasThumb2DSP() && (Mask & 0x2)) return -1; ARMARM confirms that the comment is right, and the code was wrong. llvm-svn: 244029
* Rename all references to old mailing lists to new lists.llvm.org address.Tanya Lattner2015-08-053-3/+3
| | | | llvm-svn: 243999
* wrap OptSize and MinSize attributes for easier and consistent access (NFCI)Sanjay Patel2015-08-0413-41/+29
| | | | | | | | | | | | | | | | | Create wrapper methods in the Function class for the OptimizeForSize and MinSize attributes. We want to hide the logic of "or'ing" them together when optimizing just for size (-Os). Currently, we are not consistent about this and rely on a front-end to always set OptimizeForSize (-Os) if MinSize (-Oz) is on. Thus, there are 18 FIXME changes here that should be added as follow-on patches with regression tests. This patch is NFC-intended: it just replaces existing direct accesses of the attributes by the equivalent wrapper call. Differential Revision: http://reviews.llvm.org/D11734 llvm-svn: 243994
* [x86] machine combiner reassociation: mark EFLAGS operand as 'dead'Sanjay Patel2015-08-041-4/+43
| | | | | | | | | | | | | | In the commentary for D11660, I wasn't sure if it was alright to create new integer machine instructions without also creating the implicit EFLAGS operand. From what I can see, the implicit operand is always created by the MachineInstrBuilder based on the instruction type, so we don't have to do that explicitly. However, in reviewing the debug output, I noticed that the operand was not marked as 'dead'. The machine combiner should do that to preserve future optimization opportunities that may be checking for that dead EFLAGS operand themselves. Differential Revision: http://reviews.llvm.org/D11696 llvm-svn: 243990
* [mips][FastISel] Disable code generation for unsupported targets through ↵Vasileios Kalintiris2015-08-041-0/+12
| | | | | | | | | | | | | | | | | | | FastISel. Summary: Previously, we would check whether the target is supported or not, only in fastSelectInstruction(). This means that 64-bit targets could use FastISel too. We fix this by checking every overridden method of the FastISel class and by falling back to SelectionDAG if the target isn't supported. This change should have been committed along with r243638, but somehow I missed it. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11755 llvm-svn: 243986
* Revert r229675 - [mips] Avoid redundant sign extension of the result of ↵Vasileios Kalintiris2015-08-041-8/+0
| | | | | | | | | | | | | | | | binary bitwise instructions. It introduced two regressions on 64-bit big-endian targets running under N32 (MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4, and MultiSource/Applications/kimwitu++/kc) The issue is that on 64-bit targets comparisons such as BEQ compare the whole GPR64 but incorrectly tell the instruction selector that they operate on GPR32's. This leads to the elimination of i32->i64 extensions that are actually required by comparisons to work correctly. There's currently a patch under review that fixes this problem. llvm-svn: 243984
* ARM: support windows division routinesSaleem Abdulrasool2015-08-041-0/+5
| | | | | | | | | This adds the software division routines for the Windows RTABI. These are not expected to be used often though as most modern Windows ARM capable targets support hardware division. In the case that the target CPU doesnt support hardware division, this will be the fallback. llvm-svn: 243952
* ARM: make Darwin libcall registration table driven (NFC)Saleem Abdulrasool2015-08-041-71/+65
| | | | | | | Make the libcall updating table driven similar to the approach that the Linux and Windows codepath does below. NFC. llvm-svn: 243951
* [AArch64] Rename FP formats to be more consistent. NFC.Ahmed Bougacha2015-08-042-40/+40
| | | | | | | | Some are named "FP", others "SD", others still "FP*SD". Rename all this to just use "FP", which, except for conversions (which don't use this format naming scheme), implies "SD" anyway. llvm-svn: 243936
* [AArch64] Add isel support for f16 indexed LD/ST.Ahmed Bougacha2015-08-042-0/+4
| | | | llvm-svn: 243935
* [AArch64][v8.1a] The "pan" sysreg isn't MSR-specific. NFCI.Ahmed Bougacha2015-08-041-3/+0
| | | | | | | It's already in SysRegMappings, no need to also have it in MSRMappings: the latter is only used if we didn't find a match in the former. llvm-svn: 243933
* [AArch64] Remove unnecessary "break". NFC.Ahmed Bougacha2015-08-041-1/+0
| | | | llvm-svn: 243931
* [AArch64] Use SDValue bool operator. NFC.Ahmed Bougacha2015-08-041-6/+3
| | | | llvm-svn: 243930
* [AArch64] Vector FCOPYSIGN supports Custom-lowering: mark it as such.Ahmed Bougacha2015-08-041-1/+4
| | | | | | | | | | | There's a bunch of code in LowerFCOPYSIGN that does smart lowering, and is actually already vector-aware; let's use it instead of scalarizing! The only interesting change is that for v2f32, we previously always used use v4i32 as the integer vector type. Use v2i32 instead, and mark FCOPYSIGN as Custom. llvm-svn: 243926
* ARM: remove horrible printf left over from debuggingTim Northover2015-08-031-1/+0
| | | | llvm-svn: 243907
* Convert some AArch64 code to foreach loops. NFC.Pete Cooper2015-08-035-26/+23
| | | | | | | Also converted a cast<> to dyn_cast while i was working on the same line of code. llvm-svn: 243894
* ARM: prefer allocating VFP regs at stride 4 on Darwin.Tim Northover2015-08-033-9/+27
| | | | | | | | | This is necessary for WatchOS support, where the compact unwind format assumes this kind of layout. For now we only want this on Swift-like CPUs though, where it's been the Xcode behaviour for ages. Also, since it can expand the prologue we don't want it at -Oz. llvm-svn: 243884
* [ARM] Make GlobalMerge merge extern globals by defaultJohn Brawn2015-08-031-1/+7
| | | | | | | | | | | Enabling merging of extern globals appears to be generally either beneficial or harmless. On some benchmarks suites (on Cortex-M4F, Cortex-A9, and Cortex-A57) it gives improvements in the 1-5% range, but in the rest the overall effect is zero. Differential Revision: http://reviews.llvm.org/D10966 llvm-svn: 243874
* Be less conservative about forming IT blocks.James Molloy2015-08-031-1/+1
| | | | | | | | | | | | | | | | In http://reviews.llvm.org/rL215382, IT forming was made more conservative under the belief that a flag-setting instruction was unpredictable inside an IT block on ARMv6M. But actually, ARMv6M doesn't even support IT blocks so that's impossible. In the ARMARM for v7M, v7AR and v8AR it states that the semantics of such an instruction changes inside an IT block - it doesn't set the flags. So actually it is fine to use one inside an IT block as long as the flags register is dead afterwards. This gives significant performance improvements in a variety of MPEG based workloads. Differential revision: http://reviews.llvm.org/D11680 llvm-svn: 243869
* WebAssembly: implement getScalarShiftAmountTy so we can shift by amount, ↵JF Bastien2015-08-032-0/+7
| | | | | | | | | | | | with type Summary: This currently sets the shift amount RHS to the same type as the LHS, and assumes that the LHS is a simple type. This isn't currently the case e.g. with weird integers sizes, but will eventually be true and will assert if not. That's what you get for having an experimental backend: break it and you get to keep both pieces. Most backends either set the RHS to MVT::i32 or MVT::i64, but WebAssembly is a virtual ISA and tries to have regular-looking binary operations where both operands are the same type (even if a 64-bit RHS shifter is slightly silly, hey it's free!). Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11715 llvm-svn: 243860
* De-constify pointers to Type since they can't be modified. NFCCraig Topper2015-08-0112-42/+42
| | | | | | This was already done in most places a while ago. This just fixes the ones that crept in over time. llvm-svn: 243842
* [NVPTX] allow register copy between float and intJingyue Wu2015-08-011-22/+23
| | | | | | | | | | | | | | | Summary: Fixes PR24303. With Bruno's WIP (D11197) on PeepholeOptimizer, across-class register copying (e.g. i32 to f32) becomes possible. Enhance NVPTXInstrInfo::copyPhysReg to handle these cases. Reviewers: jholewinski Subscribers: eliben, jholewinski, llvm-commits, bruno Differential Revision: http://reviews.llvm.org/D11622 llvm-svn: 243839
* -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are ↵David Blaikie2015-08-012-9/+1
| | | | | | | | | | deprecated in C++11 Remove some unnecessary explicit special members in Hexagon that, once removed, allow the other implicit special members to be used without depending on deprecated features. llvm-svn: 243825
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