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* [WebAssembly] Fix CFG stackification of nested loops.Dan Gohman2015-10-021-4/+15
| | | | llvm-svn: 249187
* [WebAssembly] Support calls marked as "tail", fastcc, and coldcc.Dan Gohman2015-10-021-4/+14
| | | | llvm-svn: 249184
* [WebAssembly] Add a resize_memory intrinsic.Dan Gohman2015-10-021-0/+8
| | | | llvm-svn: 249178
* [WebAssembly] Add a memory_size intrinsic.Dan Gohman2015-10-021-0/+8
| | | | llvm-svn: 249171
* AMDGPU/SI: Add verifier check for exec readsMatt Arsenault2015-10-022-2/+14
| | | | | | | Make sure we aren't accidentally not setting these in the instruction definitions. llvm-svn: 249170
* Actually switch the arch when we see .arch. PR21695Roman Divacky2015-10-021-0/+5
| | | | llvm-svn: 249165
* ARM: diagnose invalid local fixups on Thumb1Tim Northover2015-10-022-20/+62
| | | | | | | | | We previously stopped producing Thumb2 relaxations when they weren't supported, but only diagnosed the case where an actual relocation was produced. We should also tell people if local symbols aren't going to work rather than silently overflowing. llvm-svn: 249164
* ARM: correctly align constant pool value on Thumb1 targets.Tim Northover2015-10-021-1/+1
| | | | | | | Since we're using tLDRpci to access it, the constant pool's address must be 0 (mod 4). llvm-svn: 249163
* [ARM] Typo. NFC.Chad Rosier2015-10-021-1/+1
| | | | llvm-svn: 249153
* Reapply r249121 : "[FastISel][x86] Teach how to select SSE2/AVX bitcasts ↵Andrea Di Biagio2015-10-021-0/+24
| | | | | | | | | | | | | | | | | | | | | | | between 128/256-bit vector types." This patch teaches FastIsel the following two things: 1) On SSE2, no instructions are needed for bitcasts between 128-bit vector types; 2) On AVX, no instructions are needed for bitcasts between 256-bit vector types. Example: %1 = bitcast <4 x i31> %V to <2 x i64> Before (-fast-isel -fast-isel-abort=1): FastIsel miss: %1 = bitcast <4 x i31> %V to <2 x i64> Now we don't fall back to SelectionDAG and we correctly fold that computation propagating the register associated to %V. Originally reviewed here: http://reviews.llvm.org/D13347 llvm-svn: 249147
* Revert: [FastISel][x86] Teach how to select SSE2/AVX bitcasts between ↵Andrea Di Biagio2015-10-021-24/+0
| | | | | | | | | 128/256-bit vector types. r249121 caused a Clang test failure (avx2-buitins.c). Revert r249121 while I keep investigating on the reason why that test failed. llvm-svn: 249124
* [mips][microMIPS] Fix an issue with selecting sqrt instruction in LLVM backendZoran Jovanovic2015-10-021-5/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D13235 llvm-svn: 249123
* [FastISel][x86] Teach how to select SSE2/AVX bitcasts between 128/256-bit ↵Andrea Di Biagio2015-10-021-0/+24
| | | | | | | | | | | | | | | | | | | | | | | vector types. This patch teaches FastIsel the following two things: 1) On SSE2, no instructions are needed for bitcasts between 128-bit vector types; 2) On AVX, no instructions are needed for bitcasts between 256-bit vector types. Example: %1 = bitcast <4 x i31> %V to <2 x i64> Before (-fast-isel -fast-isel-abort=1): FastIsel miss: %1 = bitcast <4 x i31> %V to <2 x i64> Now we don't fall back to SelectionDAG and we correctly fold that computation propagating the register associated to %V. Differential Revision: http://reviews.llvm.org/D13347 llvm-svn: 249121
* AMDGPU: Fix unused variable warning in release buildMatt Arsenault2015-10-011-2/+2
| | | | llvm-svn: 249091
* AMDGPU: Move SIFixSGPRLiveRanges to be a regalloc passMatt Arsenault2015-10-012-33/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace LiveInterval usage with LiveVariables. LiveIntervals computes far more information than is needed for this pass which just needs to find if an SGPR is live out of the defining block. LiveIntervals are not usually available that early, requiring computing them twice which is very expensive. The extra run of LiveIntervals/LiveVariables/SlotIndexes was costing in total about 5% of compile time. Continuing to use LiveIntervals is problematic. It seems there is an option (early-live-intervals) to run the analysis about where it should go to avoid recomputing LiveVariables, but it seems to be completely broken with subreg liveness enabled. There are also problems from trying to recompute LiveIntervals since this seems to undo LiveVariables and clearing kill flags, causing TwoAddressInstructions to make bad decisions. Insert the pass right after live variables and preserve it. The tricky case to worry about might be phis since LiveVariables doesn't count a register as live out if in the successor block it is only used in a phi, but I don't think this is a concern right now because SIFixSGPRCopies replaces SGPR phis. llvm-svn: 249087
* Fix relocation used for GOT references in non-PIC mode. Fix relocationsJoerg Sonnenberger2015-10-011-28/+33
| | | | | | | | for "set" pseudo op in PIC mode. Differential Revision: http://reviews.llvm.org/D13173 llvm-svn: 249086
* AMDGPU: Merge if and switchMatt Arsenault2015-10-011-14/+17
| | | | llvm-svn: 249082
* AMDGPU: Remove dead codeMatt Arsenault2015-10-011-7/+4
| | | | | | | There's no point in checking VReg_1 because all uses of it should already have been removed by SILowerI1Copies. llvm-svn: 249081
* AMDGPU: Make SIInsertWaits about a factor of 4 fasterMatt Arsenault2015-10-012-23/+24
| | | | | | | | | | | | | | | | | | This was the slowest target custom pass and was spending 80% of the time in getMinimalPhysRegClass which was called for every register operand. Try to use the statically known register class when possible from the instruction's MCOperandInfo. There are a few pseudo instructions which are not well behaved with unknown register classes which still require the expensive physical register class search. There are a few other possibilities for making this even faster, such as not inspecting implicit operands. For now those are checked because it is technically possible to have a scalar load into exec or vcc which can be implicitly used. llvm-svn: 249079
* [WinEH] Emit __C_specific_handler tables for the new IRReid Kleckner2015-10-011-4/+15
| | | | | | | | | | | | We emit denormalized tables, where every range of invokes in the same state gets a complete list of EH action entries. This is significantly simpler than trying to infer the correct nested scoping structure from the MI. Fortunately, for SEH, the nesting structure is really just a size optimization. With this, some basic __try / __except examples work. llvm-svn: 249078
* AMDGPU/SI: Remove assert from AMDGPUOpenCLImageTypeLowering passTom Stellard2015-10-011-2/+6
| | | | | | | | | | | | | | | Summary: Instead of asserting when the kernel metadata is different than we expect, we should just skip lowering that function. This fixes assertion failures with OpenCL argument metadata from older LLVM releases. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D13356 llvm-svn: 249073
* [WinEH] Make FuncletLayout more robust against catchretDavid Majnemer2015-10-014-19/+38
| | | | | | | | | Catchret transfers control from a catch funclet to an earlier funclet. However, it is not completely clear which funclet the catchret target is part of. Make this clear by stapling the catchret target's funclet membership onto the CATCHRET SDAG node. llvm-svn: 249052
* [AArch64] Deprecate a command-line option used for testing.Chad Rosier2015-10-011-12/+4
| | | | | | | Support for pairing unscaled loads and stores has been enabled since the original ARM64 port. This feature is no longer experimental, AFAICT. llvm-svn: 249049
* [SystemZ] Add some generic (floating point support) load instructions.Jonas Paulsson2015-10-014-17/+37
| | | | | | | | | | | | | | | | | | | | | | Add generic instructions for load complement, load negative and load positive for fp32 and fp64, and let isel prefer them. They do not clobber CC, and so give scheduler more freedom. SystemZElimCompare pass will convert them when it can to the CC-setting variants. Regression tests updated to expect the new opcodes in places where the old ones where used. New test case SystemZ/fp-cmp-05.ll checks that SystemZCompareElim.cpp can handle the new opcodes. README.txt updated (bullet removed). Note that fp128 is not yet handled, because it is relatively rare, and is a bit trickier, because of the fact that l.dfr would operate on the sign bit of one of the subregisters of a fp128, but we would not want to copy the other sub-reg in case src and dst regs are not the same. Reviewed by Ulrich Weigand. llvm-svn: 249046
* AMDGPU: Add MEM_RAT STORE_TYPED.Tom Stellard2015-10-013-0/+23
| | | | | | | | | | | | v2: Add test (Matt). Fix capitalization of isEOP (Matt). Move pattern to class parameter (Matt). Make the instruction available to Cayman (Matt). Change name from MEM_RAT WRITE_TYPED to MEM_RAT STORE_TYPED. Patch by: Zoltan Gilian llvm-svn: 249042
* AMDGPU: Factor out EOP query.Tom Stellard2015-10-011-4/+6
| | | | | | | | v2: Fix brace placement and capitalization (Matt). Patch by: Zoltan Gilian llvm-svn: 249041
* Revert r248959, "[WinEH] Emit int3 after noreturn calls on Win64"NAKAMURA Takumi2015-10-012-23/+7
| | | | | | It broke; LLVM :: CodeGen__Generic__2009-11-16-BadKillsCrash.ll llvm-svn: 249032
* [SystemZ] Add assembly instructions for obtaining clock values as well as ↵Ulrich Weigand2015-10-011-0/+20
| | | | | | | | | | | CPU features Provide assembler support for STCK, STCKF, STCKE, and STFLE. Author: joncmu Differential Revision: http://reviews.llvm.org/D13299 llvm-svn: 249015
* [AArch64] Hoist commonly failing check. NFC.Chad Rosier2015-10-011-6/+6
| | | | llvm-svn: 249011
* [AArch64] Rename variable to improve readability. NFC.Chad Rosier2015-10-011-10/+10
| | | | llvm-svn: 249008
* [AArch64] Update comment to reflect reality.Chad Rosier2015-10-011-2/+2
| | | | llvm-svn: 249007
* [mips][microMIPS] Implement CACHEE, WRPGPR and WSBH instructionsZoran Jovanovic2015-10-013-5/+39
| | | | | | Differential Revision: http://reviews.llvm.org/D10337 llvm-svn: 249004
* [ARM] More care with Thumb1 writeback in ARMLoadStoreOptimizerScott Douglass2015-10-011-3/+7
| | | | | | Differential Revision: http://reviews.llvm.org/D13240 llvm-svn: 249002
* AMDGPU/SI: Re-order PreloadedValue enum and number entries based on init orderTom Stellard2015-10-011-9/+12
| | | | | | | | | | Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D12451 llvm-svn: 248978
* [X86] Don't custom-lower vNi32 uint_to_fp when unsafe-fp-math.Ahmed Bougacha2015-10-011-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The custom code produces incorrect results if later reassociated. Since r221657, on x86, vNi32 uitofp is lowered using an optimized sequence: movdqa LCPI0_0(%rip), %xmm1 ## xmm1 = [65535, ...] pand %xmm0, %xmm1 por LCPI0_1(%rip), %xmm1 ## [0x4b000000, ...] psrld $16, %xmm0 por LCPI0_2(%rip), %xmm0 ## [0x53000000, ...] addps LCPI0_3(%rip), %xmm0 ## [float -5.497642e+11, ...] addps %xmm1, %xmm0 Since r240361, the machine combiner opportunistically reassociates 2-instruction sequences (with -ffast-math). In the new code sequence, the ADDPS' are eligible. In isolation, for simple examples (without reassociable users), this makes no performance difference (the goal being to enable reassociation of longer chains). In the trivial example (just one uitofp), the reassociation doesn't happen, because (I think) it would require the emission of a separate movaps for a constantpool load (instead of folding it into addps). However, when we have multiple uitofp sequences, and the constantpool loads are CSE'd earlier, the machine combiner can do the reassociation. When the ADDPS' are reassociated, the resulting sequence isn't correct anymore, as we'd be adding large (2**39) constants with comparatively smaller values (~2**23). Given that two of the three inputs are powers of 2 larger than 2**16, and that ulp(2**39) == 2**(39-24) == 2**15, the reassociated chain will produce 0 for any input in [0, 2**14[. In my testing, it also produces wrong results for 99.5% of [0, 2**32[. Avoid this by disabling the new lowering when -ffast-math. It does mean that we'll get slower code than without it, but at least we won't get egregiously incorrect code. One might argue that, considering -ffast-math is all but meaningless, uitofp producing wrong results isn't a compiler bug. But it really is. Fixes PR24512. ...though this is really more of a workaround. Ideally, we'd have some sort of Machine FMF, but that's a problem that's not worth tackling until we do more with machine IR. llvm-svn: 248965
* [WinEH] Emit int3 after noreturn calls on Win64Reid Kleckner2015-09-302-7/+23
| | | | | | | | | | | | | | | | | | | | | | | The Win64 unwinder disassembles forwards from each PC to try to determine if this PC is in an epilogue. If so, it skips calling the EH personality function for that frame. Typically, this means you cannot catch an exception in the same frame that you threw it, because 'throw' calls a noreturn runtime function. Previously we avoided this problem with the TrapUnreachable TargetOption, but that's a much bigger hammer than we need. All we need is a 1 byte non-epilogue instruction right after the call. Instead, what we got was an unconditional branch to a shared block containing the ud2, potentially 7 bytes instead of 1. So, this reverts r206684, which added TrapUnreachable, and replaces it with something better. The new code pattern matches for invoke/call followed by unreachable and inserts an int3 into the DAG. To be 100% watertight, we would need to insert SEH_Epilogue instructions into all basic blocks ending in a call with no terminators or successors, but in practice this is unlikely to come up. llvm-svn: 248959
* [x86] enable machine combiner reassociations for 256-bit vector logical ↵Sanjay Patel2015-09-301-0/+3
| | | | | | integer insts llvm-svn: 248955
* Fix -Wsign-compare warningDavid Blaikie2015-09-301-1/+1
| | | | llvm-svn: 248942
* [AArch64] Remove an unnecessary restriction on pre-index instructions.Chad Rosier2015-09-301-2/+1
| | | | | | | | Previously, the index was constrained to the size of the memory operation for no apparent reason. This change removes that constraint so that we can form pre-index instructions with any valid offset. llvm-svn: 248931
* [PowerPC] Disable shrink wrappingHal Finkel2015-09-301-2/+2
| | | | | | | Shrink wrapping is causing a self-hosting failure on PPC64/Linux. Disable for now until the problem can be fixed. llvm-svn: 248924
* [ARM] Support for ARMv6-Z / ARMv6-ZK missingArtyom Skrobov2015-09-301-2/+1
| | | | | | | | | | | | | | | As Richard Barton observed at http://reviews.llvm.org/D12937#inline-107121 TargetParser in LLVM has insufficient support for ARMv6Z and ARMv6ZK. In particular, there were no tests for TrustZone being supported in these architectures. The patch clears a FIXME: left by Saleem Abdulrasool in r201471, and fixes his test case which hadn't really been testing what it was claiming to test. Differential Revision: http://reviews.llvm.org/D13236 llvm-svn: 248921
* [AArch64] Use helper function to improve readability. NFC.Chad Rosier2015-09-301-2/+1
| | | | llvm-svn: 248914
* [ARM][NEON] Use address space in vld([1234]|[234]lane) and ↵Jeroen Ketema2015-09-301-6/+7
| | | | | | | | | | | | | | | | | | | | | vst([1234]|[234]lane) instructions This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
* [X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP ↵Simon Pilgrim2015-09-306-44/+157
| | | | | | | | | | | | shift instructions The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878
* AMDGPU/SI: Don't set DATA_FORMAT if ADD_TID_ENABLE is setMarek Olsak2015-09-294-8/+18
| | | | | | | | | | to prevent setting a huge stride, because DATA_FORMAT has a different meaning if ADD_TID_ENABLE is set. This is a candidate for stable llvm 3.7. Tested-and-Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 248858
* [WinEH] Setup RBP correctly in Win64 funclet prologuesReid Kleckner2015-09-291-52/+44
| | | | | | | Previously local variable captures just didn't work in 64-bit. Now we can access local variables more or less correctly. llvm-svn: 248857
* [WinEH] Ensure that funclets obey the x64 ABIDavid Majnemer2015-09-292-38/+32
| | | | | | | | | | The x64 ABI requires that epilogues do not contain code other than stack adjustments and some limited control flow. However, we'd insert code to initialize the return address after stack adjustments. Instead, insert EAX/RAX with the current value before we create the stack adjustments in the epilogue. llvm-svn: 248839
* HHVM calling conventions.Maksim Panchenko2015-09-293-7/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | HHVM calling convention, hhvmcc, is used by HHVM JIT for functions in translated cache. We currently support LLVM back end to generate code for X86-64 and may support other architectures in the future. In HHVM calling convention any GP register could be used to pass and return values, with the exception of R12 which is reserved for thread-local area and is callee-saved. Other than R12, we always pass RBX and RBP as args, which are our virtual machine's stack pointer and frame pointer respectively. When we enter translation cache via hhvmcc function, we expect the stack to be aligned at 16 bytes, i.e. skewed by 8 bytes as opposed to standard ABI alignment. This affects stack object alignment and stack adjustments for function calls. One extra calling convention, hhvm_ccc, is used to call C++ helpers from HHVM's translation cache. It is almost identical to standard C calling convention with an exception of first argument which is passed in RBP (before we use RDI, RSI, etc.) Differential Revision: http://reviews.llvm.org/D12681 llvm-svn: 248832
* [AArch64] Add support for pre- and post-index LDPSWs.Chad Rosier2015-09-291-5/+7
| | | | llvm-svn: 248825
* [WinEH] Teach AsmPrinter about funcletsDavid Majnemer2015-09-291-2/+3
| | | | | | | | | | | Summary: Funclets have been turned into functions by the time they hit the object file. Make sure that they have decent names for the symbol table and CFI directives explaining how to reason about their prologues. Differential Revision: http://reviews.llvm.org/D13261 llvm-svn: 248824
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