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* Use explicit add_subdirectory's for LLVM target sublibraries insteadOscar Fuentes2011-02-2016-10/+41
| | | | | | | | | of testing for its presence at cmake time. This way the build automatically regenerates the makefiles when a svn update brings in a new sublibrary. llvm-svn: 126068
* Minor x86 README updates.Eli Friedman2011-02-191-20/+14
| | | | llvm-svn: 126054
* implement PR9264: disambiguating 'bt mem, imm' as a btl.Chris Lattner2011-02-191-0/+3
| | | | | | | This is reasonable to do since all bt-mem forms do the same thing. llvm-svn: 126047
* Fix typos.Eric Christopher2011-02-191-2/+2
| | | | llvm-svn: 126018
* Avoid dangling else warnings.Joerg Sonnenberger2011-02-191-1/+2
| | | | llvm-svn: 126004
* add a way to disable all builtins, wire it up to opt's ↵Chris Lattner2011-02-181-0/+6
| | | | | | -disable-simplifylibcalls flag. llvm-svn: 125978
* Move library stuff out of the toplevel CMakeLists.txt file.Oscar Fuentes2011-02-181-0/+50
| | | | llvm-svn: 125968
* introduce a new TargetLibraryInfo pass, which transformations can use toChris Lattner2011-02-183-0/+51
| | | | | | | | query about available library functions. For now this just has memset_pattern16, which exists on darwin, but it can be extended for a bunch of other things in the future. llvm-svn: 125965
* Fix style and a typoBruno Cardoso Lopes2011-02-181-4/+4
| | | | llvm-svn: 125949
* Add assembly parsing support for "msr" and also fix its encoding. Also addBruno Cardoso Lopes2011-02-187-47/+169
| | | | | | testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
* add a poor division by constant case.Chris Lattner2011-02-181-0/+37
| | | | llvm-svn: 125832
* Recognize monitor/mwait with explicit register argumentsJoerg Sonnenberger2011-02-181-0/+8
| | | | llvm-svn: 125805
* Recognize leavel and leaveq aliases for leave.Joerg Sonnenberger2011-02-171-0/+3
| | | | | | Validate encoding of leave in 64bit mode. llvm-svn: 125795
* [AVX] Recorganize X86ShuffleDecode into its own libraryDavid Greene2011-02-177-33/+116
| | | | | | | | | | | | (LLVMX86Utils.a) to break cyclic library dependencies between LLVMX86CodeGen.a and LLVMX86AsmParser.a. Previously this code was in a header file and marked static but AVX requires some additional functionality here that won't be used by all clients. Since including unused static functions causes a gcc compiler warning, keeping it as a header would break builds that use -Werror. Putting this in its own library solves both problems at once. llvm-svn: 125765
* The labyrinthine X86 backend no longer appears to requireDan Gohman2011-02-171-37/+0
| | | | | | these patterns. llvm-svn: 125759
* Triple::MinGW64 is deprecated and removed. We can use Triple::MinGW32 generally.NAKAMURA Takumi2011-02-175-8/+2
| | | | | | No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way. llvm-svn: 125747
* Fix whitespace.NAKAMURA Takumi2011-02-172-9/+9
| | | | llvm-svn: 125746
* This has been implemented.Duncan Sands2011-02-171-10/+0
| | | | llvm-svn: 125738
* add some notes on compares + binops. Remove redundant entries.Chris Lattner2011-02-171-20/+47
| | | | llvm-svn: 125702
* Add a few missed xforms from GCC PR14753Chris Lattner2011-02-161-0/+29
| | | | llvm-svn: 125681
* Swap VT and DebugLoc operands of getExtLoad() for consistency withStuart Hastings2011-02-166-9/+9
| | | | | | other getNode() methods. Radar 9002173. llvm-svn: 125665
* Remove outdated README entry.Eli Friedman2011-02-161-12/+0
| | | | llvm-svn: 125660
* Remove outdated README entry.Eli Friedman2011-02-161-16/+0
| | | | llvm-svn: 125659
* Update README entry.Eli Friedman2011-02-161-13/+6
| | | | llvm-svn: 125658
* Add support for pushsection and popsection. Patch by Joerg Sonnenberger.Rafael Espindola2011-02-161-12/+7
| | | | llvm-svn: 125629
* Some single precision VFP instructions may be executed on NEON pipeline, but ↵Evan Cheng2011-02-162-28/+160
| | | | | | not double precision ones. llvm-svn: 125624
* Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as ↵Jakob Stoklund Olesen2011-02-151-21/+15
| | | | | | | | | | | | | | | | | | | | | | | | | well. This is necessary to avoid a crash in certain tangled situations where a kill flag is first correctly moved to a merged instruction, and then needs to be moved again: STR %R0, a... STR %R0<kill>, b... First becomes: STR %R0, b... STM a, %R0<kill>, ... and then: STM a, %R0, ... STM b, %R0<kill>, ... We can now remove the kill flag from the merged STM when needed. 8960050. llvm-svn: 125591
* Spelling fix: consequtive -> consecutive.Duncan Sands2011-02-151-1/+1
| | | | llvm-svn: 125563
* Remove unused bitvectors that record ARM callee-saved registers.Bob Wilson2011-02-142-23/+0
| | | | llvm-svn: 125534
* A fail to match coprocessor number and register number must fail instead of ↵Bruno Cardoso Lopes2011-02-141-1/+0
| | | | | | assert. llvm-svn: 125521
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-1410-109/+276
| | | | | | | | | | | | - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
* Enhance ComputeMaskedBits to know that aligned frameindexesChris Lattner2011-02-133-63/+54
| | | | | | | | | | | | | | | | | have their low bits set to zero. This allows us to optimize out explicit stack alignment code like in stack-align.ll:test4 when it is redundant. Doing this causes the code generator to start turning FI+cst into FI|cst all over the place, which is general goodness (that is the canonical form) except that various pieces of the code generator don't handle OR aggressively. Fix this by introducing a new SelectionDAG::isBaseWithConstantOffset predicate, and using it in places that are looking for ADD(X,CST). The ARM backend in particular was missing a lot of addressing mode folding opportunities around OR. llvm-svn: 125470
* Add encodings and mnemonics for FXSAVE64 and FXRSTOR64.Reid Kleckner2011-02-121-0/+4
| | | | | | | | These are just FXSAVE and FXRSTOR with REX.W prefixes. These versions use 64-bit pointer values instead of 32-bit pointer values in the memory map they dump and restore. llvm-svn: 125446
* Prevent IMPLICIT_DEF/KILL to become a delay filler instruction in SPARC backend.Venkatraman Govindaraju2011-02-121-0/+3
| | | | llvm-svn: 125444
* Add a note about SSE4.1 roundss/roundsd.Benjamin Kramer2011-02-121-0/+11
| | | | llvm-svn: 125438
* AsmMatcher custom operand parser failure enhancements.Jim Grosbach2011-02-123-23/+32
| | | | | | | | | | | Teach the AsmMatcher handling to distinguish between an error custom-parsing an operand and a failure to match. The former should propogate the error upwards, while the latter should continue attempting to parse with alternative matchers. Update the ARM asm parser accordingly. llvm-svn: 125426
* Implement sdiv & udiv for <4 x i16> and <8 x i8> NEON vector types.Nate Begeman2011-02-111-0/+182
| | | | | | This avoids moving each element to the integer register file and calling __divsi3 etc. on it. llvm-svn: 125402
* Remove std::string version of getNameWithPrefix.Rafael Espindola2011-02-111-10/+0
| | | | llvm-svn: 125363
* Fix buggy fcopysign lowering.Evan Cheng2011-02-111-5/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This define float @foo(float %x, float %y) nounwind readnone { entry: %0 = tail call float @copysignf(float %x, float %y) nounwind readnone ret float %0 } Was compiled to: vmov s0, r1 bic r0, r0, #-2147483648 vmov s1, r0 vcmpe.f32 s0, #0 vmrs apsr_nzcv, fpscr it lt vneglt.f32 s1, s1 vmov r0, s1 bx lr This fails to copy the sign of -0.0f because it's lost during the float to int conversion. Also, it's sub-optimal when the inputs are in GPR registers. Now it uses integer and + or operations when it's profitable. And it's correct! lsrs r1, r1, #31 bfi r0, r1, #31, #1 bx lr rdar://8984306 llvm-svn: 125357
* [AVX] Implement 256-bit vector lowering for SCALAR_TO_VECTOR. ThisDavid Greene2011-02-101-0/+18
| | | | | | | largely completes support for 128-bit fallback lowering for code that is not 256-bit ready. llvm-svn: 125315
* Fix a lot of o32 CC issues and add a bunch of tests. Patch by Akira Hatanaka ↵Bruno Cardoso Lopes2011-02-101-47/+71
| | | | | | with some small modifications by me. llvm-svn: 125292
* [AVX] Implement 256-bit vector lowering for EXTRACT_VECTOR_ELT.David Greene2011-02-101-1/+35
| | | | llvm-svn: 125284
* ptx: add passing parameter to kernel functionsChe-Liang Chiou2011-02-108-61/+96
| | | | llvm-svn: 125279
* [AVX] Implement 256-bit vector lowering for INSERT_VECTOR_ELT.David Greene2011-02-091-6/+36
| | | | llvm-svn: 125187
* Add intrinsic for setc instruction on the XCore.Richard Osborne2011-02-091-1/+12
| | | | llvm-svn: 125186
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-088-128/+86
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127
* [AVX] Implement BUILD_VECTOR lowering for 256-bit vectors. ForDavid Greene2011-02-081-3/+64
| | | | | | | anything but the simplest of cases, lower a 256-bit BUILD_VECTOR by splitting it into 128-bit parts and recombining. llvm-svn: 125105
* Temporary workaround for a bad bug introduced by r121082 which replacedEvan Cheng2011-02-082-8/+19
| | | | | | | | | | | | t2LDRpci with t2LDRi12. There are a couple of problems with this. 1. The encoding for the literal and immediate constant are different. Note bit 7 of the literal case is 'U' so it can be negative. 2. t2LDRi12 is now narrowed to tLDRpci before constant island pass is run. So we end up never using the Thumb2 instruction, which ends up creating a lot more constant islands. llvm-svn: 125074
* Add support for parsing dmb/dsb instructionsBruno Cardoso Lopes2011-02-073-0/+65
| | | | llvm-svn: 125055
* Remove the MCR asm parser hack and start using the custom target specific asmBruno Cardoso Lopes2011-02-072-31/+106
| | | | | | | | | | | | | | | | | | parsing of operands introduced in r125030. As a small note, besides using a more generic approach we can also have more descriptive output when debugging llvm-mc, example: mcr p7, #1, r5, c1, c1, #4 note: parsed instruction: ['mcr', <ARMCC::al>, <coprocessor number: 7>, 1, <register 73>, <coprocessor register: 1>, <coprocessor register: 1>, 4] llvm-svn: 125052
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