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* Target/X86: Tweak win64's tailcall.NAKAMURA Takumi2011-01-267-12/+49
| | | | llvm-svn: 124272
* Fix whitespace.NAKAMURA Takumi2011-01-266-132/+129
| | | | llvm-svn: 124270
* lib/Target/X86/X86RegisterInfo.cpp: Fix whitespace.NAKAMURA Takumi2011-01-261-3/+3
| | | | llvm-svn: 124268
* lib/Target/X86/X86RegisterInfo.cpp: Fix a typo in comment.NAKAMURA Takumi2011-01-261-1/+1
| | | | llvm-svn: 124267
* Revert 124230. It was causing test failures.Bill Wendling2011-01-251-4/+2
| | | | llvm-svn: 124233
* The floating point value is encoded in its binary form as an Imm. Convert itBill Wendling2011-01-251-2/+4
| | | | | | appropriately so that it prints out the decimal representation. llvm-svn: 124230
* Don't merge restore with tail call instruction.Evan Cheng2011-01-251-1/+6
| | | | llvm-svn: 124167
* Provide correct registers for EH stuff on ARMAnton Korobeynikov2011-01-241-3/+4
| | | | llvm-svn: 124151
* fix a missing shuffle pattern, PR9009. Patch by Artiom Myaskouvskey!Chris Lattner2011-01-241-0/+3
| | | | llvm-svn: 124102
* this isn't a memset, we do convert dest[i] to one though :)Chris Lattner2011-01-241-8/+0
| | | | llvm-svn: 124097
* with recent work, we now optimize this into:Chris Lattner2011-01-241-20/+0
| | | | | | | | | | | define i32 @foo(i32 %x) nounwind readnone ssp { entry: %tobool = icmp eq i32 %x, 0 %tmp5 = select i1 %tobool, i32 2, i32 1 ret i32 %tmp5 } llvm-svn: 124091
* Add a memset loop that LoopIdiomRecognize doesn't recognize.Anders Carlsson2011-01-231-0/+8
| | | | llvm-svn: 124082
* Initialize MCNoExecStack.Rafael Espindola2011-01-231-0/+1
| | | | llvm-svn: 124079
* Add support for the --noexecstack option.Rafael Espindola2011-01-234-7/+12
| | | | llvm-svn: 124077
* Null initialize a few variables flagged byTed Kremenek2011-01-233-3/+3
| | | | | | | | | | clang's -Wuninitialized-experimental warning. While these don't look like real bugs, clang's -Wuninitialized-experimental analysis is stricter than GCC's, and these fixes have the benefit of being general nice cleanups. llvm-svn: 124073
* Delay the creation of eh_frame so that the user can change the defaults.Rafael Espindola2011-01-231-1/+0
| | | | | | Add support for SHT_X86_64_UNWIND. llvm-svn: 124059
* Remove more duplicated code.Rafael Espindola2011-01-235-21/+21
| | | | llvm-svn: 124056
* Remove duplicated code.Rafael Espindola2011-01-236-15/+21
| | | | llvm-svn: 124054
* Pass sret arguments through the stack instead of through registers in Sparc ↵Venkatraman Govindaraju2011-01-223-4/+75
| | | | | | backend. It makes the code generated more compliant with the sparc32 ABI. llvm-svn: 124030
* Added ICC, FCC as uses of movcc instruction to generate correct code when ↵Venkatraman Govindaraju2011-01-221-42/+51
| | | | | | -mattr=v9 is used. llvm-svn: 124027
* Sparc backend: Venkatraman Govindaraju2011-01-213-23/+28
| | | | | | | Rename FLUSH to FLUSHW. Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used. llvm-svn: 123997
* Last round of fixes for movw + movt global address codegen.Evan Cheng2011-01-219-75/+136
| | | | | | | | | | 1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. llvm-svn: 123991
* Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm",Bruno Cardoso Lopes2011-01-212-15/+24
| | | | | | | qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This is described in ARM manuals and matches the encoding used by the gnu assembler. llvm-svn: 123975
* Implement support for byval arguments in Sparc backend.Venkatraman Govindaraju2011-01-211-1/+31
| | | | llvm-svn: 123974
* Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick2011-01-211-9/+5
| | | | | | | | | | | flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
* Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relativeEvan Cheng2011-01-201-5/+1
| | | | | | | | | value, the "add pc" must be CSE'ed at the same time. We could follow the same approach as T2 by adding pseudo instructions that combine the ldr + "add pc". But the better approach is to use movw + movt (which I will enable soon), so I'll leave this as a TODO. llvm-svn: 123949
* Fix the encoding and parsing of clrex instructionBruno Cardoso Lopes2011-01-202-5/+9
| | | | llvm-svn: 123936
* Change instruction names for consistencyBruno Cardoso Lopes2011-01-201-4/+6
| | | | llvm-svn: 123930
* Add cdp/cdp2 instructions for thumb/thumb2Bruno Cardoso Lopes2011-01-203-1/+51
| | | | llvm-svn: 123929
* - Use a more appropriate name for Owen's ARM Parser isMCR hack since the ↵Bruno Cardoso Lopes2011-01-202-26/+60
| | | | | | | | | | same operands can be present in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions. - Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t hem. llvm-svn: 123927
* Add mcr*2 and mr*c2 support to thumb2 targetsBruno Cardoso Lopes2011-01-202-0/+62
| | | | llvm-svn: 123919
* Add mcr* and mr*c support to thumb targetsBruno Cardoso Lopes2011-01-203-2/+68
| | | | llvm-svn: 123917
* Allow sign-extending of i8 and i16 to i128 on SPU. Kalle Raiskila2011-01-202-1/+7
| | | | llvm-svn: 123912
* Refactor mcr* and mr*c instructions into classes with the same encoding. No ↵Bruno Cardoso Lopes2011-01-201-108/+46
| | | | | | functionality change. llvm-svn: 123910
* Correct itinerary entry for t2MOV_pic_ga_add_pc.Evan Cheng2011-01-201-1/+1
| | | | llvm-svn: 123907
* Sorry, several patches in one.Evan Cheng2011-01-2012-168/+275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
* Sparc backend: Implements a delay slot filler that attempt to fill delay slotsVenkatraman Govindaraju2011-01-202-8/+225
| | | | | | with useful instructions. llvm-svn: 123884
* Fix the encoding of mrrc and mcrr family of instructions. Also add testcases ↵Bruno Cardoso Lopes2011-01-191-16/+16
| | | | | | for mcr and mrc llvm-svn: 123837
* ARM/ISel: Factor out isScaledConstantInRange() helper.Daniel Dunbar2011-01-191-122/+110
| | | | llvm-svn: 123823
* For ARM subtargets with useNEONForSinglePrecisionFP, double count usesAndrew Trick2011-01-191-0/+16
| | | | | | | | of the floating point types less than 64-bits. It's somewhat of a temporary hack but forces more accurate modeling of register pressure and results in fewer spills. llvm-svn: 123811
* whitespaceAndrew Trick2011-01-191-16/+16
| | | | llvm-svn: 123810
* Don't forget to emit the load from indirect symbol when using movw + movt to ↵Evan Cheng2011-01-194-6/+14
| | | | | | materialize GA indirect symbols. llvm-svn: 123809
* Create two new generic classes to represent the following VMRS/VMSR variations:Bruno Cardoso Lopes2011-01-182-30/+55
| | | | | | | | | vmrs reg, fpexc vmrs reg, fpsid vmsr fpexc, reg vmsr fpsid, reg llvm-svn: 123783
* Fix MRS encoding for arm and thumb.Bruno Cardoso Lopes2011-01-182-4/+9
| | | | llvm-svn: 123778
* Fix the encoding of t2ISB by using the right class and also parse it correctlyBruno Cardoso Lopes2011-01-182-2/+2
| | | | llvm-svn: 123776
* Follow the current hack set and enable the correct parsing of bkpt while in ↵Bruno Cardoso Lopes2011-01-181-3/+9
| | | | | | thumb mode. llvm-svn: 123772
* Add support for parsing and encoding ARM's official syntax for the BFI ↵Bruno Cardoso Lopes2011-01-184-13/+79
| | | | | | instruction llvm-svn: 123770
* Add a FIXME.Jim Grosbach2011-01-181-0/+1
| | | | llvm-svn: 123769
* Ensure Mips::GP is properly reloaded after a function call. Patch by Sasa ↵Bruno Cardoso Lopes2011-01-182-0/+9
| | | | | | Stankovic llvm-svn: 123768
* Negative zero is not legal on mips. Patch by Sasa StankovicBruno Cardoso Lopes2011-01-181-0/+2
| | | | llvm-svn: 123766
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