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* Codegen floating point stores of constants into integer instructions. ThisChris Lattner2004-05-071-15/+37
| | | | | | | | | | | | | | | | | | | allows us to compile: store float 10.0, float* %P into: mov DWORD PTR [%EAX], 1092616192 instead of: .CPItest_0: # float 0x4024000000000000 .long 1092616192 # float 10 ... fld DWORD PTR [.CPItest_0] fstp DWORD PTR [%EAX] llvm-svn: 13409
* Make comparisons against the null pointer as efficient as integer comparisonsChris Lattner2004-05-071-1/+8
| | | | | | | | | | | | | against zero. In particular, don't emit: mov %ESI, 0 cmp %ECX, %ESI instead, emit: test %ECX, %ECX llvm-svn: 13407
* Missing piece of fix for Bug 333Brian Gaeke2004-05-041-1/+1
| | | | llvm-svn: 13362
* Correctly mangle function names when they are used as part of aBrian Gaeke2004-05-041-3/+3
| | | | | | | | | constant pool member's name. This is intended to address Bug 333. Also, fix an anachronistic usage of "M" as a parameter of type Function *. llvm-svn: 13357
* Remove unneeded checkChris Lattner2004-05-041-1/+0
| | | | llvm-svn: 13355
* Improve signed division by power of 2 *dramatically* from this:Chris Lattner2004-05-041-9/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | div: mov %EDX, DWORD PTR [%ESP + 4] mov %ECX, 64 mov %EAX, %EDX sar %EDX, 31 idiv %ECX ret to this: div: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, %EAX sar %ECX, 5 shr %ECX, 26 mov %EDX, %EAX add %EDX, %ECX sar %EAX, 6 ret Note that the intel compiler is currently making this: div: movl 4(%esp), %edx #3.5 movl %edx, %eax #4.14 sarl $5, %eax #4.14 shrl $26, %eax #4.14 addl %edx, %eax #4.14 sarl $6, %eax #4.14 ret #4.14 Which has one less register->register copy. (hint hint alkis :) llvm-svn: 13354
* Improve code generated for integer multiplications by 2,3,5,9Chris Lattner2004-05-041-2/+16
| | | | llvm-svn: 13342
* Remove unused #includeChris Lattner2004-05-011-1/+0
| | | | llvm-svn: 13304
* Iterate over the Machine CFG that Brian added instead of the LLVM CFG.Chris Lattner2004-05-011-21/+4
| | | | | | Look at all of the pretty minuses. :) llvm-svn: 13303
* Add a constructor that got lostChris Lattner2004-05-011-0/+3
| | | | llvm-svn: 13297
* Removing MachineResource class.Tanya Lattner2004-04-301-1/+1
| | | | llvm-svn: 13291
* Make RequiresFPRegKill() take a MachineBasicBlock arg.Brian Gaeke2004-04-281-3/+3
| | | | | | | In InsertFPRegKills(), just check the MachineBasicBlock for successors instead of its corresponding BasicBlock. llvm-svn: 13213
* In InsertFPRegKills(), use the machine-CFG itself rather than theBrian Gaeke2004-04-281-3/+3
| | | | | | LLVM CFG when trying to find the successors of BB. llvm-svn: 13212
* Update the machine-CFG edges whenever we see a branch.Brian Gaeke2004-04-281-0/+5
| | | | llvm-svn: 13211
* Integrate the rest of my random sparcv9 scribblings into this fileBrian Gaeke2004-04-271-2/+3
| | | | llvm-svn: 13204
* Changes to fix up the inst_iterator to pass to boost iterator checks. ThisChris Lattner2004-04-272-9/+9
| | | | | | patch was graciously contributed by Vladimir Prus. llvm-svn: 13185
* Fix file header comments and include guards -- many files have been moved orBrian Gaeke2004-04-2530-54/+67
| | | | | | | renamed since they were last spiffed up, or they just never had proper comments in the first place. llvm-svn: 13148
* Add a getRegisterInfo() accessor just like on the X86 target.Brian Gaeke2004-04-251-0/+3
| | | | llvm-svn: 13147
* Regularize file header comment and include guard.Brian Gaeke2004-04-251-3/+12
| | | | | | | | Include SparcV9RegisterInfo.h. Add a getRegisterInfo() accessor and SparcV9RegisterInfo instance, just like on the X86 target. llvm-svn: 13146
* Add MRegisterInfo subclass for the SparcV9 target (containing only stubBrian Gaeke2004-04-252-0/+420
| | | | | | | | | | | | functions for now). This automatically turns on the printing of machine registers using their own real names, instead of goofy things like %mreg(42), and allows us to migrate code incrementally to the new interface as we see fit. The register file description it uses is hand-written, so that the register numbers will match the ones that the SparcV9 target already uses. Perhaps someday we'll tablegen it. llvm-svn: 13145
* Fix a typo.Brian Gaeke2004-04-231-2/+1
| | | | llvm-svn: 13136
* Merge TargetRegInfo.h into SparcV9RegInfo.h, which is its only subclass.Brian Gaeke2004-04-231-5/+280
| | | | | | | | This prepares us to be able to de-virtualize and de-abstract it, and take the register allocator bits out and move them into the register allocator proper... llvm-svn: 13127
* Include SparcV9RegInfo.h instead of TargetRegInfo.h.Brian Gaeke2004-04-2310-10/+10
| | | | llvm-svn: 13126
* Get rid of the old byte-at-a-time emission code used when the Sparc JIT wasBrian Gaeke2004-04-231-9/+0
| | | | | | being tested on X86, as per Chris's request. llvm-svn: 13124
* Use emitWordAt() to emit forward-branch fixups.Brian Gaeke2004-04-231-1/+1
| | | | llvm-svn: 13120
* Emit SPARC machine code a word at a time instead of a byte at a time.Brian Gaeke2004-04-231-1/+5
| | | | | | Use emitWordAt() to emit forward-branch fixups. llvm-svn: 13119
* Make SparcV9RegInfo::getRegType() return the right answer for registersBrian Gaeke2004-04-211-5/+6
| | | | | | | | | of IntCC, FloatCC, and Special types. Make SparcV9RegInfo::getRegClassIDOfRegType() return the right answer if you ask for the class corresponding to SpecialRegType. llvm-svn: 13095
* Make it legal to ask for the type of a specialregBrian Gaeke2004-04-201-0/+2
| | | | llvm-svn: 13078
* Make it legal to request a load or store of %fsr.Brian Gaeke2004-04-191-0/+2
| | | | llvm-svn: 13073
* Regularize include guards and remove some excess whitespace.Brian Gaeke2004-04-191-4/+2
| | | | llvm-svn: 13071
* Tighten up SparcV9FloatCCRegClass::getRegName()'s assertion - if you ask it forBrian Gaeke2004-04-191-2/+1
| | | | | | | the name of %fsr (as the comment in SparcV9RegClassInfo.h used to suggest) you would walk off the end of the FloatCCRegName array. llvm-svn: 13070
* Regularize include guards, remove some excess whitespace and fix some comments.Brian Gaeke2004-04-191-14/+11
| | | | | | Remove the extra %fsr register from SparcV9FloatCCRegClass. llvm-svn: 13069
* Give SparcV9CodeEmitter a head-of-file comment and a PassName.Brian Gaeke2004-04-151-1/+6
| | | | llvm-svn: 12967
* Remove code to adjust the iterator for llvm.readio and llvm.writeio.John Criswell2004-04-141-10/+0
| | | | | | | The iterator is pointing at the next instruction which should not disappear when doing the load/store replacement. llvm-svn: 12954
* Fix typo.Brian Gaeke2004-04-141-1/+1
| | | | llvm-svn: 12953
* This is the real fix for Codegen/X86/2004-04-13-FPCMOV-Crash.llx which worksChris Lattner2004-04-141-7/+8
| | | | | | | | | | | | | | | | | even when the "optimization" I added before is turned off. It generates this extremely pointless code: test: fld QWORD PTR [%ESP + 4] mov %AL, 0 test %AL, %AL fcmove %ST(0), %ST(0) ret Good thing the optimizer will have removed this before code generation anyway. :) llvm-svn: 12939
* Added support for the llvm.readio and llvm.writeio intrinsics.John Criswell2004-04-131-0/+29
| | | | | | | On x86, memory operations occur in-order, so these are just lowered into volatile loads and stores. llvm-svn: 12936
* Implement a small optimization, which papers over the problem inChris Lattner2004-04-131-3/+12
| | | | | | | | X86/2004-04-13-FPCMOV-Crash.llx A more robust fix is to follow. llvm-svn: 12935
* I don't think we have to have 4 extra allocated (but unused) bytes on the stack.Brian Gaeke2004-04-132-2/+2
| | | | llvm-svn: 12905
* I started working on casts, but I don't have anything compilable yet.Brian Gaeke2004-04-131-0/+11
| | | | llvm-svn: 12903
* Emit the immediate form of in/out when possible.Chris Lattner2004-04-131-49/+82
| | | | | | | | | | | Fix several bugs in the intrinsics: 1. Make sure to copy the input registers before the instructions that use them 2. Make sure to copy the value returned by 'in' out of EAX into the register it is supposed to be in. This fixes assertions when using in/out and linear scan. llvm-svn: 12896
* Add immediate forms of in/out. Use let to shorten linesChris Lattner2004-04-131-7/+19
| | | | llvm-svn: 12895
* Add support for new instruction typeChris Lattner2004-04-131-0/+2
| | | | llvm-svn: 12894
* Add support for the printImplicitDefsBefore flagChris Lattner2004-04-133-7/+38
| | | | llvm-svn: 12893
* We don't need to insert TargetData into the PassManager here.Brian Gaeke2004-04-121-5/+0
| | | | llvm-svn: 12874
* Fix issues that the local allocator has dealing with instructions that ↵Chris Lattner2004-04-123-9/+14
| | | | | | implicitly use ST(0) llvm-svn: 12855
* No really, fix printing for LLC. I gotta get a way for CVS to whine at me ifChris Lattner2004-04-121-1/+1
| | | | | | I have unsaved emacs buffers, geeze... llvm-svn: 12854
* Correct printing for LLC and the encoding for the JITChris Lattner2004-04-121-3/+4
| | | | llvm-svn: 12853
* Use the fucomi[p] instructions to perform floating point comparisons insteadChris Lattner2004-04-121-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of the fucom[p][p] instructions. This allows us to code generate this function bool %test(double %X, double %Y) { %C = setlt double %Y, %X ret bool %C } ... into: test: fld QWORD PTR [%ESP + 4] fld QWORD PTR [%ESP + 12] fucomip %ST(1) fstp %ST(0) setb %AL movsx %EAX, %AL ret where before we generated: test: fld QWORD PTR [%ESP + 4] fld QWORD PTR [%ESP + 12] fucompp ** fnstsw ** sahf setb %AL movsx %EAX, %AL ret The two marked instructions (which are the ones eliminated) are very bad, because they serialize execution of the processor. These instructions are available on the PPRO and later, but since we already use cmov's we aren't losing any portability. I retained the old code for the day when we decide we want to support back to the 386. llvm-svn: 12852
* Add support for the FUCOMIr instructionChris Lattner2004-04-121-27/+34
| | | | llvm-svn: 12851
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