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* Move the ARM reloc constants to Support/ELF.hJason W Kim2010-11-232-142/+4
| | | | llvm-svn: 120035
* Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations.Bob Wilson2010-11-231-13/+109
| | | | | | | We need to check if the individual vector elements are sign/zero-extended values. For now this only handles constants values. Radar 8687140. llvm-svn: 120034
* InstCombine: Reduce "X shift (A srem B)" to "X shift (A urem B)" iff B is ↵Benjamin Kramer2010-11-231-10/+2
| | | | | | | | positive. This allows to transform the rem in "1 << ((int)x % 8);" to an and. llvm-svn: 120028
* Division by pow-of-2 is not cheap on SPU, do it with Kalle Raiskila2010-11-231-2/+0
| | | | | | shifts. llvm-svn: 120022
* Implement the rex64 prefix.Rafael Espindola2010-11-232-1/+5
| | | | llvm-svn: 120017
* Produce a relocation for pcrel absolute values. Based on a patch by David Meyer.Rafael Espindola2010-11-231-8/+12
| | | | llvm-svn: 120006
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-2314-605/+604
| | | | llvm-svn: 119990
* Remove duplicated constants. Thanks to Jason for noticing it.Rafael Espindola2010-11-222-42/+26
| | | | llvm-svn: 119985
* InstCombine: Implement X - A*-B -> X + A*B.Benjamin Kramer2010-11-221-16/+0
| | | | llvm-svn: 119984
* Fix epilogue codegen to avoid leaving the stack pointer in an invalidEvan Cheng2010-11-223-23/+50
| | | | | | | | | | | | | | | | | state. Previously Thumb2 would restore sp from fp like this: mov sp, r7 sub, sp, #4 If an interrupt is taken after the 'mov' but before the 'sub', callee-saved registers might be clobbered by the interrupt handler. Instead, try restoring directly from sp: add sp, #4 Or, if necessary (with VLA, etc.) use a scratch register to compute sp and then restore it: sub.w r4, r7, #8 mov sp, r7 rdar://8465407 llvm-svn: 119977
* Fix a bug with extractelement on SPU.Kalle Raiskila2010-11-221-1/+1
| | | | | | | In the attached testcase, the element was never extracted (missing rotate). llvm-svn: 119973
* Implement the "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" optimization.Benjamin Kramer2010-11-221-10/+0
| | | | | | | This currently only catches the most basic case, a two-case switch, but can be extended later. llvm-svn: 119964
* Fix a compiler warning about Kind being used uninitializedDuncan Sands2010-11-221-1/+1
| | | | | | when assertions are disabled. llvm-svn: 119962
* Pseudos default to 4byte size, let the instruction size field noticeEric Christopher2010-11-211-1/+3
| | | | | | that branch tables are special. llvm-svn: 119954
* Implement ELF object file writing support for the MBlaze backend. Its not ↵Wesley Peck2010-11-215-111/+104
| | | | | | perfect yet, but it works for many tests. llvm-svn: 119952
* Implement branch analysis in the MBlaze backend.Wesley Peck2010-11-212-46/+201
| | | | llvm-svn: 119951
* Make it a little bit more explicit that the MBlaze backend only supports uptoWesley Peck2010-11-212-3/+3
| | | | | | 32-bit immediate values. llvm-svn: 119950
* Fix an error in the MBlaze delay slot filler where instructions that alreadyWesley Peck2010-11-211-16/+29
| | | | | | fill a delay slot are moved to fill a different delay slot. llvm-svn: 119949
* apparently tailcalls are better on darwin/x86-64 than on linux?Chris Lattner2010-11-211-0/+18
| | | | llvm-svn: 119947
* More Thumb encodings.Bill Wendling2010-11-211-25/+82
| | | | llvm-svn: 119940
* Add encoding for ARM "trap" instruction.Bill Wendling2010-11-211-4/+1
| | | | llvm-svn: 119938
* The "trap" instruction is one of this which doesn't have a condition code. HackBill Wendling2010-11-211-2/+5
| | | | | | the code to not add a "condition code" if it's trap. llvm-svn: 119937
* - Give "trap" the correct encoding, at least according to Darwin's assembler.Bill Wendling2010-11-211-3/+10
| | | | | | - Add comments saying where the encodings for other instructions came from. llvm-svn: 119936
* implement PR8524, apparently mainline gas accepts movq as an alias for movdChris Lattner2010-11-211-0/+4
| | | | | | when transfering between i64 gprs and mmx regs. llvm-svn: 119931
* add some random notes.Chris Lattner2010-11-211-2/+33
| | | | llvm-svn: 119925
* Use by-name rather than by-order operand matching for some NEON encodings.Owen Anderson2010-11-211-34/+34
| | | | llvm-svn: 119923
* optimize:Chris Lattner2010-11-211-8/+0
| | | | | | | | | void a(int x) { if (((1<<x)&8)==0) b(); } into "x != 3", which occurs over 100 times in 403.gcc but in no other program in llvm-test. llvm-svn: 119922
* tail calls on x86 are implemented.Chris Lattner2010-11-211-16/+0
| | | | llvm-svn: 119920
* BR_JTadd is ARM-only, so use the proper pseudo class to get the predicate.Jim Grosbach2010-11-211-1/+1
| | | | llvm-svn: 119918
* A few more thumb instruction MC encodings.Bill Wendling2010-11-201-16/+38
| | | | llvm-svn: 119913
* Rewrite address handling to use a structure with all the possible addressEric Christopher2010-11-201-11/+76
| | | | | | mode variables. Handle frame indexes in load/store and allocas again. llvm-svn: 119912
* STRH only needs the additional operand, not t2STRH. Also invert conditionalEric Christopher2010-11-201-9/+5
| | | | | | to match the one from the load emitter above. llvm-svn: 119911
* Make this compile on case-sensitive file systemswAnton Korobeynikov2010-11-201-2/+2
| | | | llvm-svn: 119905
* Move some more hooks to TargetFrameInfoAnton Korobeynikov2010-11-2014-171/+186
| | | | llvm-svn: 119904
* On X86, MEMBARRIER, MFENCE, SFENCE, LFENCE are not target memory intrinsics,Duncan Sands2010-11-201-6/+6
| | | | | | | | | | | so don't claim they are. They are allocated using DAG.getNode, so attempts to access MemSDNode fields results in reading off the end of the allocated memory. This fixes crashes with "llc -debug" due to debug code trying to print MemSDNode fields for these barrier nodes (since the crashes are not deterministic, use valgrind to see this). Add some nasty checking to try to catch this kind of thing in the future. llvm-svn: 119901
* Add more Thumb add instruction encodings.Bill Wendling2010-11-201-12/+47
| | | | llvm-svn: 119883
* Add Thumb encodings for some add instructions.Bill Wendling2010-11-201-6/+26
| | | | llvm-svn: 119882
* Add more encodings for Thumb instructions.Bill Wendling2010-11-201-15/+30
| | | | llvm-svn: 119881
* Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the sameBill Wendling2010-11-201-9/+21
| | | | | | value that the one in ARMMCCodeEmitter.cpp does. llvm-svn: 119878
* Fix ARM LDR* post-indexed operand encoding.Jim Grosbach2010-11-191-5/+5
| | | | llvm-svn: 119869
* Encodings for the compare instructions.Bill Wendling2010-11-191-8/+19
| | | | llvm-svn: 119868
* The Vm and Vn register fields must be the same for a register-register vmov.Owen Anderson2010-11-191-2/+6
| | | | llvm-svn: 119867
* Fix a cut-n-paste-error.Evan Cheng2010-11-191-1/+1
| | | | llvm-svn: 119866
* Operand namesJim Grosbach2010-11-191-4/+4
| | | | llvm-svn: 119864
* trailing whitespaceJim Grosbach2010-11-191-16/+16
| | | | llvm-svn: 119863
* Don't need to save piecemeal now.Eric Christopher2010-11-191-4/+2
| | | | llvm-svn: 119862
* Update comment.Eric Christopher2010-11-191-3/+2
| | | | llvm-svn: 119861
* Add encodings for some of the thumb ADD instructions. Tests will come once theBill Wendling2010-11-191-16/+44
| | | | | | asm parser can handle them. llvm-svn: 119860
* Update comment.Eric Christopher2010-11-191-1/+1
| | | | llvm-svn: 119859
* Clarify operand names.Jim Grosbach2010-11-191-3/+3
| | | | llvm-svn: 119858
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