summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* Typos.Chad Rosier2012-10-032-5/+4
| | | | llvm-svn: 165141
* Add methods which query for the specific attribute instead of using theBill Wendling2012-10-032-16/+16
| | | | | | enums. This allows for better encapsulation of the Attributes class. llvm-svn: 165132
* Set up MCSchedModel after detecting the CPU type in X86SubTarget.Preston Gurd2012-10-031-0/+4
| | | | | | | | | Corrects a problem whereby MCSchedModel was not being set up when the CPU type was auto-detected. Patch by Andy Zhang. llvm-svn: 165122
* Revert 165051-165049 while looking into the foreach.m failure inEric Christopher2012-10-032-12/+9
| | | | | | more detail. llvm-svn: 165099
* Fix 80-column violationCraig Topper2012-10-031-2/+2
| | | | llvm-svn: 165089
* The early if conversion pass is ready to be used as an opt-in.Jakob Stoklund Olesen2012-10-031-1/+7
| | | | | | | | | | | Enable the pass by default for targets that request it, and change the -enable-early-ifcvt to the opposite -disable-early-ifcvt. There are still some x86 regressions when enabling early if-conversion because of the missing machine models. Disable the pass for x86 until machine models are added. llvm-svn: 165075
* Fix a serious X86 instruction selection bug. InEvan Cheng2012-10-021-3/+14
| | | | | | | | | | | | | X86DAGToDAGISel::PreprocessISelDAG(), isel is moving load inside callseq_start / callseq_end so it can be folded into a call. This can create a cycle in the DAG when the call is glued to a copytoreg. We have been lucky this hasn't caused too many issues because the pre-ra scheduler has special handling of call sequences. However, it has caused a crash in a specific tailcall case. rdar://12393897 llvm-svn: 165072
* Revert "Don't use a debug location for frame setup instructions in the"Eric Christopher2012-10-021-0/+2
| | | | | | | This reverts 165055 and 165052 temporarily while I look at debugger failures. llvm-svn: 165071
* Revert 165057, per Jim's request. This requires further discussion.Chad Rosier2012-10-021-26/+8
| | | | llvm-svn: 165069
* The mips 64bit instructions DSLL, DSRA, DSRL, DEXT and DINS get transformed ↵Jack Carter2012-10-026-56/+54
| | | | | | | | | | | | by the assembler or through codegen direct object output to other variants based on the value of the immediate values of the operands. If the code is generated as assembler, this transformation does not occur assuming that it will occur later in the assembler. This code was originally called from MipsAsmPrinter.cpp and we needed to check for OutStreamer.hasRawTextSupport(). This was not a good place for it and has been moved to MCTargetDesc/MipsMCCodeEmitter.cpp where both direct object and the assembler use it it automagically. The test cases have been checked in for a number of weeks now. llvm-svn: 165067
* Make sure to put our sret argument into %rax on x86-64. Fixes PR13563!Nick Lewycky2012-10-021-2/+16
| | | | llvm-svn: 165063
* [ms-inline asm] Add basic support for wildcard MCParsedAsmOperands. This typeChad Rosier2012-10-021-8/+26
| | | | | | | | | | | | | of operand is specific to MS-style inline assembly and should not be generated when parsing normal assembly. The purpose of the wildcard operands are to allow the AsmParser to match multiple instructions (i.e., MCInsts) to a given ms-style asm statement. For the time being the matcher just returns the first match. This patch only implements wildcard matches for memory operands. Support for register wildcards will be added in the near future. llvm-svn: 165057
* Don't use a debug location for frame setup instructions in theEric Christopher2012-10-021-2/+0
| | | | | | | prologue. Also skip frame setup instructions when looking for the first location. llvm-svn: 165052
* Use the existing DebugLoc.Eric Christopher2012-10-021-1/+1
| | | | llvm-svn: 165051
* Make the location a parameter since we may not want the next oneEric Christopher2012-10-021-7/+10
| | | | | | in the block. llvm-svn: 165050
* Remove the SavePoint infrastructure from fast isel, replaceEric Christopher2012-10-021-2/+2
| | | | | | | with just an insert point from the MachineBasicBlock and let the location be updated as we access it. llvm-svn: 165049
* Support for generating ELF objects on Windows.Andrew Kaylor2012-10-023-8/+15
| | | | | | This adds 'elf' as a recognized target triple environment value and overrides the default generated object format on Windows platforms if that value is present. This patch also enables MCJIT tests on Windows using the new environment value. llvm-svn: 165030
* [ms-inline asm] Add the convertToMapAndConstraints() function that is used toChad Rosier2012-10-014-35/+47
| | | | | | | | | | | map constraints and MCInst operands to inline asm operands. This replaces the getMCInstOperandNum() function. The logic to determine the constraints are not in place, so we still default to a register constraint (i.e., "r"). Also, we no longer build the MCInst but rather return just the opcode to get the MCInstrDesc. llvm-svn: 164979
* MachO: direct-to-object attribute for data-in-code markers.Jim Grosbach2012-10-011-1/+3
| | | | | | | | | | The target backend can support data-in-code load commands even when the assembler doesn't, or vice-versa. Allow targets to opt-in for direct-to-object. PR13973. llvm-svn: 164974
* Use constants for all return values in switch. Allows clang to optimize it ↵Craig Topper2012-10-011-3/+8
| | | | | | into a lookup table. llvm-svn: 164926
* Change getX86SubSuperRegister to take an MVT::SimpleValueType rather than an ↵Craig Topper2012-09-304-11/+12
| | | | | | EVT and add llvm_unreachable to the switches. Helps it compile to dramatically better code. llvm-svn: 164919
* Add LLVM support for Swift.Bob Wilson2012-09-2918-63/+1810
| | | | llvm-svn: 164899
* Whitespace.Bob Wilson2012-09-291-1/+1
| | | | llvm-svn: 164898
* Shrink TargetAlignElem a bit, we do a lot of searches on them.Benjamin Kramer2012-09-291-0/+2
| | | | llvm-svn: 164897
* MIPS DSP: other miscellaneous instructions.Akira Hatanaka2012-09-282-0/+136
| | | | llvm-svn: 164845
* MIPS DSP: ADDUH.QB instruction sub-class.Akira Hatanaka2012-09-282-0/+112
| | | | llvm-svn: 164840
* X86: when replacing SUB with TEST in ISelDAGToDAG, only replace uses of theManman Ren2012-09-281-5/+28
| | | | | | | | second output of SUB with first output of TEST. PR13966 llvm-svn: 164835
* 1. Add load/store words from the stackReed Kotler2012-09-283-34/+86
| | | | | | | | | 2. As part of this, added assembly format FEXT_RI16_SP_explicit_ins and moved other lines for FEXT_RI16 formats to be in the right place in the code. 3. Added mayLoad and mayStore assignements for the load/store instructions added and for ones already there that did not have this assignment. 4. Another patch will deal with the problem of load/store byte/halfword to the stack. This is a particular Mips16 problem. llvm-svn: 164811
* MIPS DSP: ABSQ_S.PH instruction sub-class.Akira Hatanaka2012-09-272-0/+162
| | | | llvm-svn: 164787
* MIPS DSP: SHLL.QB instruction sub-class.Akira Hatanaka2012-09-272-0/+151
| | | | llvm-svn: 164786
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru2012-09-2711-18/+18
| | | | | | See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-2711-18/+18
| | | | llvm-svn: 164767
* [arm-fast-isel] Add support for ELF PIC.Jush Lu2012-09-275-2/+123
| | | | | | | This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. llvm-svn: 164759
* MIPS DSP: rddsp (instruction which reads DSPControl register fields to a GPR).Akira Hatanaka2012-09-272-0/+26
| | | | llvm-svn: 164756
* MIPS DSP: CMPU.EQ.QB instruction sub-class.Akira Hatanaka2012-09-272-0/+224
| | | | llvm-svn: 164755
* MIPS DSP: ADDU.QB instruction sub-class.Akira Hatanaka2012-09-272-0/+195
| | | | llvm-svn: 164754
* MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos ↵Akira Hatanaka2012-09-274-0/+103
| | | | | | Field instruction. llvm-svn: 164751
* MIPS DSP: all the remaining instructions which read or write accumulators.Akira Hatanaka2012-09-273-0/+444
| | | | llvm-svn: 164750
* MIPS DSP: add support for extract-word instructions.Akira Hatanaka2012-09-274-0/+224
| | | | llvm-svn: 164749
* MIPS DSP: add functions which decode DSP and accumulator registers.Akira Hatanaka2012-09-271-0/+29
| | | | llvm-svn: 164748
* MIPS DSP: add code necessary for pseudo instruction lowering.Akira Hatanaka2012-09-275-2/+22
| | | | llvm-svn: 164747
* MIPS DSP: add bitcast patterns between vectors and int.Akira Hatanaka2012-09-271-0/+10
| | | | | | No test cases. These patterns will get tested along with dsp intrinsics. llvm-svn: 164746
* MIPS DSP: add vector load/store patterns.Akira Hatanaka2012-09-272-0/+18
| | | | llvm-svn: 164744
* Remove the `hasFnAttr' method from Function.Bill Wendling2012-09-2612-20/+20
| | | | | | | The hasFnAttr method has been replaced by querying the Attributes explicitly. No intended functionality change. llvm-svn: 164725
* X86_32: Large Symbol+Offset relocations.Jim Grosbach2012-09-261-8/+40
| | | | | | | | | | If the offset is more than 24-bits, it won't fit in a scattered relocation offset field, so we fall back to using a non-scattered relocation. rdar://12358909 llvm-svn: 164724
* Add case clauses for returning dsp accumulator encoding values in functionAkira Hatanaka2012-09-261-2/+4
| | | | | | getMipsRegisterNumbering. llvm-svn: 164720
* Add DSP accumulator registers and register class. Remove hi/lo registers.Akira Hatanaka2012-09-261-33/+9
| | | | llvm-svn: 164719
* Delete member MipsFunctionInfo::OutArgFIRange and code that accesses it.Akira Hatanaka2012-09-263-31/+8
| | | | llvm-svn: 164718
* Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.James Molloy2012-09-261-2/+2
| | | | llvm-svn: 164685
* Add SARX/SHRX/SHLX code generation supportMichael Liao2012-09-262-0/+61
| | | | llvm-svn: 164675
OpenPOWER on IntegriCloud