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* [mips][mips16] Re-work the inline assembly stubs to work with IAS. NFC.Daniel Sanders2015-10-211-89/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Previously, we were inserting an InlineAsm statement for each line of the inline assembly. This works for GAS but it triggers prologue/epilogue emission when IAS is in use. This caused: .set noreorder .cpload $25 to be emitted as: .set push .set reorder .set noreorder .set pop .set push .set reorder .cpload $25 .set pop which led to assembler errors and caused the test to fail. The whitespace-after-comma changes included in this patch are necessary to match the output when IAS is in use. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13653 llvm-svn: 250895
* [mips][msa] Remove copy_u.d and move copy_u.w to MSA64.Daniel Sanders2015-10-213-5/+32
| | | | | | | | | | | | | | | | | | | | | | | Summary: The forwards compatibility strategy employed by MIPS is to consider registers to be infinitely sign-extended. Then on ISA's with a wider register, the result of existing instructions are sign-extended to register width and zero-extended counterparts are added. copy_u.w on MSA32 and copy_u.w on MSA64 violate this strategy and we have therefore corrected the MSA specs to fix this. We still keep track of sign/zero-extension during legalization but we now match copy_s.[wd] where required. No change required to clang since __builtin_msa_copy_u_[wd] will map to copy_s.[wd] where appropriate for the target. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13472 llvm-svn: 250887
* Do not use `dyn_cast<X>` after `isa<X>` (NFC)Mehdi Amini2015-10-211-1/+1
| | | | | From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 250883
* WebAssembly: support importsJF Bastien2015-10-211-1/+23
| | | | | | C/C++ code can declare an extern function, which will show up as an import in WebAssembly's output. It's expected that the linker will resolve these, and mark unresolved imports as call_import (I have a patch which does this in wasmate). llvm-svn: 250875
* [Hexagon] Bit-based instruction simplificationKrzysztof Parzyszek2015-10-203-0/+2793
| | | | | | | Analyze bit patterns of operands and values of instructions to perform various simplifications, dead/redundant code elimination, etc. llvm-svn: 250868
* [Hexagon] Fix isNVStorable flag in .td filesKrzysztof Parzyszek2015-10-202-20/+48
| | | | | | | An upper half and a double word cannot be used as value sources in a new-value store. llvm-svn: 250867
* [Hexagon] Capture aggregate variables by reference, not valueKrzysztof Parzyszek2015-10-201-1/+1
| | | | llvm-svn: 250851
* [Hexagon] Do not fall-through if there is no CFG edgeKrzysztof Parzyszek2015-10-201-1/+1
| | | | llvm-svn: 250850
* [Hexagon] Use symbolic name for subregister instead of hardcoded numberKrzysztof Parzyszek2015-10-201-1/+1
| | | | llvm-svn: 250849
* [Hexagon] Change Based->Base in getBasedWithImmOffsetKrzysztof Parzyszek2015-10-202-3/+3
| | | | llvm-svn: 250848
* [Hexagon] Remove the remnants of isConstExtProfitableKrzysztof Parzyszek2015-10-207-125/+27
| | | | llvm-svn: 250845
* [SystemZ] Use LivePhysRegs helper class in SystemZShortenInst.cpp.Jonas Paulsson2015-10-201-80/+35
| | | | | | | | | Don't use home brewed liveness tracking code for phys regs, since this class does the job. Reviewed by Ulrich Weigand. llvm-svn: 250829
* Adding support for TargetLoweringBase::LibCallArtyom Skrobov2015-10-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: TargetLoweringBase::Expand is defined as "Try to expand this to other ops, otherwise use a libcall." For ISD::UDIV and ISD::SDIV, the choice between the two possibilities was defined in a rather convoluted way: - if DIVREM is legal, expand to DIVREM - if DIVREM has a custom lowering, expand to DIVREM - if DIVREM libcall is defined and a remainder from the same division is computed elsewhere, expand to a DIVREM libcall - else, expand to a DIV libcall This had the undesirable effect that if both DIV and DIVREM are implemented as libcalls, then ISD::UDIV and ISD::SDIV are expanded to the heavier DIVREM libcall, even when the remainder isn't used. The new code adds a new LegalizeAction, TargetLoweringBase::LibCall, so that backends can directly control whether they prefer an expansion or a conversion to a libcall. This makes the generic lowering code even more generic, allowing its reuse in a wider range of target-specific configurations. The useful effect is that ARM backend will now generate a call to __aeabi_{i,u}div rather than __aeabi_{i,u}divmod in cases where it doesn't need the remainder. There's no functional change outside the ARM backend. Reviewers: t.p.northover, rengolin Subscribers: t.p.northover, llvm-commits, aemerson Differential Revision: http://reviews.llvm.org/D13862 llvm-svn: 250826
* AVX512: Implemented encoding and intrinsics for VPBROADCASTB/W/D/Q instructions.Igor Breger2015-10-203-106/+109
| | | | | | Differential Revision: http://reviews.llvm.org/D13884 llvm-svn: 250819
* AMDGPU: Add MachineInstr overloads for instruction format testsMatt Arsenault2015-10-207-40/+111
| | | | llvm-svn: 250797
* AMDGPU: Stop reserving v[254:255]Matt Arsenault2015-10-201-4/+0
| | | | | | | | | | | This wasn't doing anything useful. They weren't explicitly used anywhere, and the RegScavenger ignores reserved registers. This for some reason caused a random scheduling change in the test. Getting the check lines to pass is too frustrating, and there's probably not too much value in checking the vector case's operands N times. llvm-svn: 250794
* WebAssembly: fix call/return syntax.JF Bastien2015-10-201-1/+6
| | | | | | They are now typeless, unlike other operations. llvm-svn: 250793
* MSP430: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-202-5/+3
| | | | llvm-svn: 250792
* SystemZ: Remove implicit ilist iterator conversion, NFCDuncan P. N. Exon Smith2015-10-201-1/+1
| | | | llvm-svn: 250790
* XCore: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-202-8/+4
| | | | llvm-svn: 250788
* PowerPC: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-205-27/+23
| | | | llvm-svn: 250787
* Sparc: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-202-5/+4
| | | | llvm-svn: 250781
* NVPTX: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-207-25/+20
| | | | llvm-svn: 250779
* Hexagon: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-2016-38/+34
| | | | | | | | | | | | | | | | | | | There are two things out of the ordinary in this commit. First, I made a loop obviously "infinite" in HexagonInstrInfo.cpp. After checking if an instruction was at the beginning of a basic block (in which case, `break`), the loop decremented and checked the iterator for `nullptr` as the loop condition. This has never been possible (the prev pointers are always been circular, so even with the weird ilist/iplist implementation, this isn't been possible), so I removed the condition. Second, in HexagonAsmPrinter.cpp there was another case of comparing a `MachineBasicBlock::instr_iterator` against `MachineBasicBlock::end()` (which returns `MachineBasicBlock::iterator`). While not incorrect, it's fragile. I switched this to `::instr_end()`. All that said, no functionality change intended here. llvm-svn: 250778
* WebAssembly: fix syntax for br_if.JF Bastien2015-10-203-5/+5
| | | | llvm-svn: 250777
* Mips: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-209-40/+29
| | | | llvm-svn: 250769
* CppBackend: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-201-37/+26
| | | | | | | Mostly just converted to range-based for loops. May have converted a couple of extra loops as a drive-by (not sure). llvm-svn: 250766
* BPF: Remove implicit ilist iterator conversion, NFCDuncan P. N. Exon Smith2015-10-201-2/+1
| | | | llvm-svn: 250765
* ARM: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-199-45/+40
| | | | llvm-svn: 250759
* X86: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-198-31/+24
| | | | llvm-svn: 250741
* [Hexagon] Remove unnecessary argument sign extendsKrzysztof Parzyszek2015-10-193-0/+155
| | | | llvm-svn: 250724
* Add missing override noticed by Clang's -Winconsistent-missing-override.Benjamin Kramer2015-10-191-1/+1
| | | | llvm-svn: 250720
* [AArch64]Merge halfword loads into a 32-bit loadJun Bum Lim2015-10-191-45/+215
| | | | | | | | | | | | | Convert two halfword loads into a single 32-bit word load with bitfield extract instructions. For example : ldrh w0, [x2] ldrh w1, [x2, #2] becomes ldr w0, [x2] ubfx w1, w0, #16, #16 and w0, w0, #ffff llvm-svn: 250719
* [Hexagon] Fix debug information for local objectsKrzysztof Parzyszek2015-10-194-117/+170
| | | | | | | | | | | | - Isolate the check for the existence of a stack frame into hasFP. - Implement getFrameIndexReference for DWARF address computation. - Use getFrameIndexReference for offset computation in eliminateFrameIndex. - Preserve debug information for dynamically allocated stack objects. - Prefer FP to access local objects at -O0. - Add experimental code to skip allocframe when not strictly necessary (disabled by default). llvm-svn: 250718
* [Hexagon] Delay emission of CFI instructionsKrzysztof Parzyszek2015-10-193-98/+178
| | | | | | | Emit the CFI instructions after all code transformation have been done. This will avoid any interference between CFI instructions and packetization. llvm-svn: 250714
* Remove CRLF newlines. NFC.Benjamin Kramer2015-10-191-6/+6
| | | | llvm-svn: 250698
* Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructionsAsiri Rathnayake2015-10-191-4/+4
| | | | | | | | | | | | | The mapping of these two intrinsics in ARMInstrInfo.td had a small omission which lead to their operands not being validated/transformed before being lowered into usat and ssat instructions. This can cause incorrect instructions to be emitted. I've also added tests for the remaining two saturating arithmatic intrinsics @llvm.arm.qadd and @llvm.arm.qsub as they are missing codegen tests. llvm-svn: 250697
* Removed parameter "Consecutive" from isLegalMaskedLoad() / isLegalMaskedStore().Elena Demikhovsky2015-10-192-14/+11
| | | | | | | | | | Originally I planned to use the same interface for masked gather/scatter and set isConsecutive to "false" in this case. Now I'm implementing masked gather/scatter and see that the interface is inconvenient. I want to add interfaces isLegalMaskedGather() / isLegalMaskedScatter() instead of using the "Consecutive" parameter in the existing interfaces. Differential Revision: http://reviews.llvm.org/D13850 llvm-svn: 250686
* [mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ↵Zlatko Buljan2015-10-193-21/+62
| | | | | | | | ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions Differential Revision: http://reviews.llvm.org/D13130 llvm-svn: 250685
* [mips][microMIPS] Implement ABSQ.QB, ABSQ_S.PH, ABSQ_S.W, ABSQ_S.QB, INSV, ↵Zlatko Buljan2015-10-193-10/+76
| | | | | | | | MADD, MADDU, MSUB, MSUBU, MULT and MULTU instructions Differential Revision: http://reviews.llvm.org/D13721 llvm-svn: 250683
* [X86][AVX512DQ] add scalar fpclassAsaf Badouh2015-10-184-6/+61
| | | | | | Differential Revision: http://reviews.llvm.org/D13769 llvm-svn: 250650
* AVX512: Lowering i8/i16 vector CTLZ using the dword LZCNT vector instructionIgor Breger2015-10-182-23/+123
| | | | | | Differential Revision: http://reviews.llvm.org/D13632 llvm-svn: 250649
* [Sparc] Use MCPhysReg instead of unsigned to size static arrays of ↵Craig Topper2015-10-181-6/+7
| | | | | | registers. Should reduce the table size. llvm-svn: 250644
* Make a bunch of static arrays const.Craig Topper2015-10-1812-28/+32
| | | | llvm-svn: 250642
* Use std::find instead of manual loop.Craig Topper2015-10-171-5/+2
| | | | llvm-svn: 250624
* Use std::is_sorted to replace a custom version. Also replace a comparison ↵Craig Topper2015-10-172-16/+4
| | | | | | predicate struct with a lambda. llvm-svn: 250623
* [X86][XOP] Add VPROT instruction opcodesSimon Pilgrim2015-10-175-33/+32
| | | | | | Added X86ISD opcodes for VPROT vector rotate by variable and by immediate. llvm-svn: 250620
* Remove unnecessary 'const' pointed out by David Blaikie.Craig Topper2015-10-171-2/+2
| | | | llvm-svn: 250619
* Replace a custom table sort check with std::is_sorted. Change a function to ↵Craig Topper2015-10-171-17/+8
| | | | | | take ArrayRef instead of pointer and length. NFC llvm-svn: 250615
* Use std::begin/end and std::is_sorted to simplify some code. NFCCraig Topper2015-10-171-8/+5
| | | | llvm-svn: 250614
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