summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* [FastISel][X86] Extend support for {s|u}{add|sub|mul}.with.overflow intrinsics.Juergen Ributzka2014-06-101-30/+89
| | | | llvm-svn: 210610
* Use unique_ptr for X86Subtarget pointer members.Eric Christopher2014-06-102-22/+16
| | | | llvm-svn: 210606
* Move AArch64TargetLowering to AArch64Subtarget.Eric Christopher2014-06-106-9/+13
| | | | | | | This currently necessitates a TargetMachine for the TargetLowering constructor and TLOF. llvm-svn: 210605
* Move AArch64InstrInfo to AArch64Subtarget.Eric Christopher2014-06-104-6/+9
| | | | llvm-svn: 210599
* Remove a method that was just replacing direct access to a member.Eric Christopher2014-06-102-20/+18
| | | | llvm-svn: 210598
* Remove the use of TargetMachine from X86InstrInfo.Eric Christopher2014-06-103-61/+60
| | | | llvm-svn: 210596
* Move X86RegisterInfo away from using the TargetMachine and onlyEric Christopher2014-06-105-33/+30
| | | | | | using the subtarget. llvm-svn: 210595
* Use the TargetMachine on the DAG or the MachineFunction insteadEric Christopher2014-06-101-82/+80
| | | | | | of using the cached TargetMachine. llvm-svn: 210589
* R600/SI: Emit an error when attempting to spill VGPRs v4Tom Stellard2014-06-101-10/+24
| | | | | | | | | | | | | | | | | | I can't get VGPR spilling to work reliable, so for now just emit an error when the register allocator tries to spill VGPRs. v2: - Fix build v3: - Added crash fix when spilling SPGRs v4: - Use V_MOV_B32 as a dummy instruction instead of S_NOP Patch by: Darren Powell https://bugs.freedesktop.org/show_bug.cgi?id=75276 llvm-svn: 210588
* R600/SI: Fix a crash when spilling SGPRsTom Stellard2014-06-102-11/+8
| | | | | | | | | | | We need to make sure only one new instruction is added when spilling otherwise the register allocator may crash. This fixes a crash in the game Antichamber. https://bugs.freedesktop.org/show_bug.cgi?id=75276 llvm-svn: 210587
* R600: Use BCNT_INT for evergreenMatt Arsenault2014-06-104-5/+16
| | | | llvm-svn: 210569
* R600/SI: Implement i64 ctpopMatt Arsenault2014-06-105-1/+64
| | | | llvm-svn: 210568
* R600/SI: Use bcnt instruction for ctpopMatt Arsenault2014-06-106-11/+27
| | | | llvm-svn: 210567
* R600: Handle fcopysignMatt Arsenault2014-06-105-3/+27
| | | | llvm-svn: 210564
* R600/SI: Handle sign_extend and zero_extend to i64 with patterns.Matt Arsenault2014-06-103-42/+36
| | | | llvm-svn: 210563
* Add a FIXME.Eric Christopher2014-06-101-0/+2
| | | | llvm-svn: 210559
* Move AArch64SelectionDAGInfo down to the subtarget.Eric Christopher2014-06-104-4/+6
| | | | llvm-svn: 210557
* Remove the cached little endian variable. We can get it easily offEric Christopher2014-06-102-7/+4
| | | | | | of the DataLayout. llvm-svn: 210555
* Have AArch64SelectionDAGInfo take a DataLayout parameter ratherEric Christopher2014-06-103-4/+4
| | | | | | than a TargetMachine. llvm-svn: 210554
* Remove caching of the subtarget for AArch64SelectionDAGInfo.Eric Christopher2014-06-102-7/+4
| | | | llvm-svn: 210553
* Move DataLayout onto the AArch64 subtarget.Eric Christopher2014-06-104-11/+15
| | | | llvm-svn: 210552
* Move AArch64FrameLowering into the subtarget.Eric Christopher2014-06-104-5/+11
| | | | llvm-svn: 210549
* Remove the uses of AArch64TargetMachine and AArch64Subtarget fromEric Christopher2014-06-105-16/+9
| | | | | | AArch64FrameLowering. llvm-svn: 210548
* Do Materialize Floating Point in Mips Fast-IselReed Kotler2014-06-101-2/+23
| | | | | | | | | | | | | | | | | Summary: Implement materialize of floating point literals in Mips Fast-Isel Reopened version of D3659 Test Plan: simplestorefp1.ll Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4071 llvm-svn: 210546
* [X86] Improved target combine rules for selecting horizontal add/sub.Andrea Di Biagio2014-06-101-2/+20
| | | | | | | | | | | | | This patch slightly changes the algorithm introduced at revision 210477 to fix a problem where the algorithm was producing incorrect code for the VEX.256 encoded versions of horizontal add/sub. For these cases, we now try to split the two 256-bit vectors into 128-bit chunks before emitting horizontal add/sub dag nodes. Added a new test case into haddsub-2.ll. llvm-svn: 210545
* Hexagon: Expand i1 SELECT_CCTom Stellard2014-06-101-0/+1
| | | | | | | | il is legal for Hexagon, so I should have marked this as Expand for SELECT_CC when I removed setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in r210541. llvm-svn: 210544
* [X86] AVX512: Add vmovntdqaAdam Nemet2014-06-101-0/+11
| | | | | | Along with the corresponding intrinsic and tests. llvm-svn: 210543
* Fix a bug in the Thumb1 ARM Load/Store optimizerRenato Golin2014-06-101-7/+7
| | | | | | | | | | | | | | Previously, the basic block was searched for future uses of the base register, and if necessary any writeback to the base register was reset using a SUB instruction (e.g. before calling a function) just before such a use. However, this step happened *before* the merged LDM/STM instruction was built. So if there was (e.g.) a function call directly after the not-yet-formed LDM/STM, the pass would first insert a SUB instruction to reset the base register, and then (at the same location, incorrectly) insert the LDM/STM itself. This patch fixes PR19972. Patch by Moritz Roth. llvm-svn: 210542
* SelectionDAG: Don't use MVT::Other to determine legality of ISD::SELECT_CCTom Stellard2014-06-105-12/+17
| | | | | | | | | | | | | The SelectionDAG bad a special case for ISD::SELECT_CC, where it would allow targets to specify: setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); to indicate that they wanted to expand ISD::SELECT_CC for all types. This wasn't applied correctly everywhere, and it makes writing new DAG patterns with ISD::SELECT_CC difficult. llvm-svn: 210541
* SelectionDAG: Expand SELECT_CC to SELECT + SETCCTom Stellard2014-06-106-51/+7
| | | | | | | | This consolidates code from the Hexagon, R600, and XCore targets. No functionality change intended. llvm-svn: 210539
* [PPC64LE] Recognize shufflevector patterns for little endianBill Schmidt2014-06-103-84/+151
| | | | | | | | | | | | | | | | | Various masks on shufflevector instructions are recognizable as specific PowerPC instructions (vector pack, vector merge, etc.). There is existing code in PPCISelLowering.cpp to recognize the correct patterns for big endian code. The masks for these instructions are different for little endian code due to the big-endian numbering employed by these instructions. This patch adds the recognition code for little endian. I've added a new test case test/CodeGen/PowerPC/vec_shuffle_le.ll for this. The existing recognizer test (vec_shuffle.ll) is unnecessarily verbose and difficult to read, so I felt it was better to add a new test rather than modify the old one. llvm-svn: 210536
* [AArch64] Emit .ident compiler version attribute.Chad Rosier2014-06-101-0/+2
| | | | | | Patch by Ana Pazos<apazos@codeaurora.org>! llvm-svn: 210535
* Condition codes AL and NV are invalid in the aliases that useArtyom Skrobov2014-06-102-1/+10
| | | | | | | | | | | | | | inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM). Matching aliases based on "immediate classes", when disassembling, wasn't previously supported, hence adding MCOperandPredicate into class Operand, and implementing the support for it in AsmWriterEmitter. The parsing for those aliases was already custom, so just adding the missing condition into AArch64AsmParser::parseCondCode. llvm-svn: 210528
* AArch64: disallow x30 & x29 as the destination for indirect tail callsTim Northover2014-06-101-1/+1
| | | | | | | | As Ana Pazos pointed out, these have to be restored to their incoming values before a function returns; i.e. before the tail call. So they can't be used correctly as the destination register. llvm-svn: 210525
* Revert "X86: elide comparisons after cmpxchg instructions."Tim Northover2014-06-102-106/+57
| | | | | | | This reverts commit r210523. It was committed prematurely without waiting for review. llvm-svn: 210524
* X86: elide comparisons after cmpxchg instructions.Tim Northover2014-06-102-57/+106
| | | | | | | | | | | | | | | The C++ and C semantics of the compare_and_swap operations actually require us to return a boolean "success" value. In LLVM terms this means a second comparison of the output of "cmpxchg" against the input desired value. However, x86's "cmpxchg" instruction sets all flags for the comparison formed, so we can skip any secondary comparison. (N.b. this isn't true for cmpxchg8b/16b, which only set ZF). rdar://problem/13201607 llvm-svn: 210523
* AArch64: teach FastISel how to handle offset FrameIndicesTim Northover2014-06-101-4/+11
| | | | | | | | | | Previously we were abandonning the attempt, leading to some combination of extra work (when selection of a load/store fails completely) and inferior code (when this leads to a real memcpy call instead of inlining). rdar://problem/17187463 llvm-svn: 210520
* AArch64: make FastISel memcpy emission more robust.Tim Northover2014-06-101-3/+5
| | | | | | | | | | We were hitting an assert if FastISel couldn't create the load or store we requested. Currently this happens for large frame-local addresses, though CodeGen could be improved there. rdar://problem/17187463 llvm-svn: 210519
* Delete X86JITInfo in the subtarget destructor.Eric Christopher2014-06-101-0/+1
| | | | llvm-svn: 210516
* [ConstantHoisting][X86] Improve the cost model for small constants with ↵Juergen Ributzka2014-06-101-8/+35
| | | | | | | | | | | large types (i64 and above). This improves the X86 cost model for small constants with large types. Before this commit we would even hoist trivial constants such as i96 2. This is related to <rdar://problem/17070936> llvm-svn: 210504
* [PPC64LE] Generate correct code for unaligned little-endian vector loadsBill Schmidt2014-06-091-21/+39
| | | | | | | | | | | | | | | | | | | The code in PPCTargetLowering::PerformDAGCombine() that handles unaligned Altivec vector loads generates a lvsl followed by a vperm. As we've seen in numerous other places, the vperm instruction has a big-endian bias, and this is fixed for little endian by complementing the permute control vector and swapping the input operands. In this case the lvsl is providing the permute control vector. Rather than generating an lvsl and a complement operation, it is sufficient to generate an lvsr instruction instead. Thus for LE code generation we will generate an lvsr rather than an lvsl, and swap the other input arguments on the vperm. The existing test/CodeGen/PowerPC/vec_misalign.ll is updated to test the code generation for PPC64 and PPC64LE, in addition to the existing PPC32/G5 testing. llvm-svn: 210493
* ARM: add VLA extension for WoA Itanium ABISaleem Abdulrasool2014-06-093-1/+125
| | | | | | | | | | | | | | | | The armv7-windows-itanium environment is nearly identical to the MSVC ABI. It has a few divergences, mostly revolving around the use of the Itanium ABI for C++. VLA support is one of the extensions that are amongst the set of the extensions. This adds support for proper VLA emission for this environment. This is somewhat similar to the handling for __chkstk emission on X86 and the large stack frame emission for ARM. The invocation style for chkstk is still controlled via the -mcmodel flag to clang. Make an explicit note that this is an extension. llvm-svn: 210489
* Move all of the x86 subtarget initialized variables down into the x86 subtargetEric Christopher2014-06-097-67/+95
| | | | | | from the x86 target machine. Should be no functional change. llvm-svn: 210479
* R600/SI: Rename VOP3 helper class to be more generalMatt Arsenault2014-06-092-4/+4
| | | | | | It has other uses besides shift instructions. llvm-svn: 210478
* [X86] Add target combine rules for horizontal add/sub.Andrea Di Biagio2014-06-091-0/+85
| | | | | | | | | | | | | | | | | | | | This patch adds new target specific combine rules to identify horizontal add/sub idioms from BUILD_VECTOR dag nodes. This patch also teaches the DAGCombiner how to canonicalize sequences of insert_vector_elt dag nodes according to the following rule: (insert_vector_elt (insert_vector_elt A, I0), I1) -> (insert_vecto_elt (insert_vector_elt A, I1), I0) This new canonicalization rule only triggers if the inner insert_vector dag node has exactly one use; also, both indices must be known constants, and I1 < I0. This last rule made it possible to write a simpler algorithm to identify horizontal add/sub patterns because now we don't have to worry about the ordering of insert_vector_elt dag nodes. llvm-svn: 210477
* R600/SI: Keep 64-bit not on SALUMatt Arsenault2014-06-093-10/+69
| | | | llvm-svn: 210476
* R600: Fix selection failure for vector bswapMatt Arsenault2014-06-091-0/+1
| | | | llvm-svn: 210475
* [PPC64LE] Generate correct little-endian code for v16i8 multiplyBill Schmidt2014-06-091-4/+16
| | | | | | | | | | | | | | | | The existing code in PPCTargetLowering::LowerMUL() for multiplying two v16i8 values assumes that vector elements are numbered in big-endian order. For little-endian targets, the vector element numbering is reversed, but the vmuleub, vmuloub, and vperm instructions still assume big-endian numbering. To account for this, we must adjust the permute control vector and reverse the order of the input registers on the vperm instruction. The existing test/CodeGen/PowerPC/vec_mul.ll is updated to be executed on powerpc64 and powerpc64le targets as well as the original powerpc (32-bit) target. llvm-svn: 210474
* [mips] Fix a bug for NaCl target - Don't report the error when non-dangerousSasa Stankovic2014-06-091-7/+6
| | | | | | | | load/store is in branch delay slot. Differential Revision: http://llvm-reviews.chandlerc.com/D4048 llvm-svn: 210470
* [X86] Avoid emitting unnecessary test instructions.Andrea Di Biagio2014-06-091-2/+19
| | | | | | | | | | | | | This patch teaches the backend how to check for the 'NoSignedWrap' flag on binary operations to improve the emission of 'test' instructions. If the result of a binary operation is known not to overflow we know that resetting the Overflow flag is unnecessary and so we can avoid emitting the test instruction. Patch by Marcello Maggioni. llvm-svn: 210468
OpenPOWER on IntegriCloud