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* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-035-125/+238
| | | | llvm-svn: 191874
* Add patterns for selecting TBM instructions from logical operations. Patch ↵Craig Topper2013-10-032-32/+98
| | | | | | from Yunzhong Gao. llvm-svn: 191871
* R600: Add a ldptr intrinsic to support MSAA.Vincent Lejeune2013-10-023-1/+10
| | | | llvm-svn: 191838
* AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 targetElena Demikhovsky2013-10-022-8/+5
| | | | llvm-svn: 191818
* AVX-512: Added TB prefix to all instructions without prefixes,Elena Demikhovsky2013-10-022-20/+18
| | | | | | otherwise encoding fails after the last change in X86MCCodeEmitter.cpp. llvm-svn: 191812
* R600: add a pass that merges clauses.Vincent Lejeune2013-10-017-2/+232
| | | | llvm-svn: 191790
* R600: Put PRED_X instruction in its own clauseVincent Lejeune2013-10-011-0/+8
| | | | llvm-svn: 191789
* R600: Enable -verify-machineinstrs in some tests.Vincent Lejeune2013-10-015-9/+19
| | | | llvm-svn: 191788
* [SystemZ] Add comparisons of high words and memoryRichard Sandiford2013-10-013-2/+30
| | | | llvm-svn: 191777
* [SystemZ] Add comparisons of large immediates using high wordsRichard Sandiford2013-10-012-2/+20
| | | | | | | There are no corresponding patterns for small immediates because they would prevent the use of fused compare-and-branch instructions. llvm-svn: 191775
* [SystemZ] Add immediate addition involving high wordsRichard Sandiford2013-10-014-2/+76
| | | | llvm-svn: 191774
* [SystemZ] Extend test-under-mask support to high GR32sRichard Sandiford2013-10-014-8/+27
| | | | llvm-svn: 191773
* [SystemZ] Extend 32-bit RISBG optimizations to high wordsRichard Sandiford2013-10-011-8/+16
| | | | | | | This involves using RISB[LH]G, whereas the equivalent z10 optimization uses RISBG. llvm-svn: 191770
* [SystemZ] Extend pseudo conditional 8- and 16-bit stores to high wordsRichard Sandiford2013-10-012-6/+22
| | | | | | As the comment says, we always want to use STOC for 32-bit stores. llvm-svn: 191767
* ARM: support interrupt attributeTim Northover2013-10-018-21/+148
| | | | | | | | | | | This function-attribute modifies the callee-saved register list and function epilogue (specifically the return instruction) so that a routine is suitable for use as an interrupt-handler of the specified type without disrupting user-mode applications. rdar://problem/14207019 llvm-svn: 191766
* [SystemZ] Optimize 32-bit FPR<->GPR moves for z196 and aboveRichard Sandiford2013-10-011-7/+18
| | | | | | | | Floats are stored in the high 32 bits of an FPR, and the only GPR<->FPR transfers are full-register transfers. This patch optimizes GPR<->FPR float transfers when the high word of a GPR is directly accessible. llvm-svn: 191764
* [SystemZ] Allow integer AND involving high wordsRichard Sandiford2013-10-015-63/+107
| | | | llvm-svn: 191762
* [SystemZ] Allow integer XOR involving high wordsRichard Sandiford2013-10-014-5/+15
| | | | llvm-svn: 191759
* Remove several unused variables.Rafael Espindola2013-10-012-4/+0
| | | | | | Patch by Alp Toker. llvm-svn: 191757
* [SystemZ] Allow integer OR involving high wordsRichard Sandiford2013-10-014-13/+41
| | | | llvm-svn: 191755
* [SystemZ] Allow integer insertions with a high-word destinationRichard Sandiford2013-10-014-2/+43
| | | | llvm-svn: 191753
* [SystemZ] Allow selects with a high-word destinationRichard Sandiford2013-10-012-2/+4
| | | | llvm-svn: 191751
* [SystemZ] Add patterns to load a constant into a high word (IIHF)Richard Sandiford2013-10-017-5/+59
| | | | | | | Similar to low words, we can use the shorter LLIHL and LLIHH if it turns out that the other half of the GR64 isn't live. llvm-svn: 191750
* [ARM] Remove an unused function from the disassembler.Joey Gouly2013-10-011-11/+0
| | | | | | Pointed out by Joerg. llvm-svn: 191749
* Test commit. Updated comment.Matheus Almeida2013-10-011-1/+1
| | | | llvm-svn: 191748
* [SystemZ] Add register zero extensions involving at least one high wordRichard Sandiford2013-10-013-2/+29
| | | | llvm-svn: 191746
* [ARM] Introduce the 'sevl' instruction in ARMv8.Joey Gouly2013-10-015-29/+22
| | | | | | | This also removes the restriction on the immediate field of the 'hint' instruction. llvm-svn: 191744
* [SystemZ] Add truncating high-word stores (STCH and STHH)Richard Sandiford2013-10-012-4/+24
| | | | llvm-svn: 191743
* [SystemZ] Add zero-extending high-word loads (LLCH and LLHH)Richard Sandiford2013-10-012-2/+22
| | | | llvm-svn: 191742
* [SystemZ] Add sign-extending high-word loads (LBH and LHH)Richard Sandiford2013-10-012-2/+22
| | | | llvm-svn: 191740
* [SystemZ] Use upper words of GR64s for codegenRichard Sandiford2013-10-0110-13/+184
| | | | | | | | | | | | | | This just adds the basics necessary for allocating the upper words to virtual registers (move, load and store). The move support is parameterised in a way that makes it easy to handle zero extensions, but the associated zero-extend patterns are added by a later patch. The easiest way of testing this seemed to be add a new "h" register constraint for high words. I don't expect the constraint to be useful in real inline asms, but it should work, so I didn't try to hide it behind an option. llvm-svn: 191739
* [SystemZ] Reapply: Add definitions of LFH and STFHRichard Sandiford2013-10-011-0/+4
| | | | | | | Originally committed as r191661, but reverted because it changed the matching order of comparisons on some hosts. That should have been fixed by r191735. llvm-svn: 191738
* [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not ↵Daniel Sanders2013-10-012-9/+23
| | | | | | intrinsics) llvm-svn: 191737
* This patch adds aliases for Mips sub instruction with immediate operands. ↵Vladimir Medic2013-10-012-2/+38
| | | | | | Corresponding test cases are added. llvm-svn: 191734
* AVX-512: Added X86vzmovl patternsElena Demikhovsky2013-10-011-0/+5
| | | | llvm-svn: 191733
* Remove 0 as a valid encoding for the m-mmmm field.Craig Topper2013-10-011-2/+0
| | | | llvm-svn: 191732
* Remove unneeded fields from disassembler internal instruction format.Craig Topper2013-10-012-20/+0
| | | | llvm-svn: 191731
* BEXTR should be defined to take same type for bother operands.Craig Topper2013-10-011-1/+1
| | | | llvm-svn: 191728
* Forgot to add a break statement.Preston Gurd2013-09-301-0/+1
| | | | llvm-svn: 191715
* The X86FixupLEAs pass for Intel Atom must not call convertToThreeAddressPreston Gurd2013-09-301-0/+8
| | | | | | | | | | | on ADD16rr opcodes, if src1 != src, since that would cause convertToThreeAddress to try to create a virtual register. This is not permitted after register allocation, which is when the X86FixupLEAs pass runs. This patch fixes PR16785. llvm-svn: 191711
* [mips][msa] Direct Object Emission for I8 instructions.Jack Carter2013-09-302-28/+39
| | | | | | | | | This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
* [mips][msa] Direct Object Emission for I5 instructions.Jack Carter2013-09-302-49/+64
| | | | | | | | | This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
* [ARM] Clean up ARMAsmParser::validateInstruction().Tilmann Scheller2013-09-301-38/+36
| | | | | | | | Fix some LLVM Coding Standards violations. No changes in functionality. llvm-svn: 191686
* [mips][msa] Direct Object Emission for 2R instructions.Jack Carter2013-09-302-16/+21
| | | | | | | | | This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}. Patch by Matheus Almeida llvm-svn: 191685
* [PATCH 1/4] [mips][msa] Source register of FILL instructions is GPRJack Carter2013-09-302-15/+26
| | | | | | | | and not an MSA register Patch by Matheus Almeida llvm-svn: 191684
* [ARM] Assembler: ARM LDRD with writeback requires the base register to be ↵Tilmann Scheller2013-09-301-4/+19
| | | | | | | | | | different from the destination registers. See ARM ARM A8.8.72. Violating this constraint results in unpredictable behavior. llvm-svn: 191678
* Swift model: Fix uop description on some writesArnold Schwaighofer2013-09-301-2/+11
| | | | | | Those writes really need two/three uops. llvm-svn: 191677
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-304-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 llvm-svn: 191671
* [SystemZ] Revert r191661: Add definitions of LFH and STFHRichard Sandiford2013-09-301-4/+0
| | | | | | | | For some reason, adding definitions for these load and store instructions changed whether some of the build bots matched comparisons as signed or unsigned. llvm-svn: 191663
* [SystemZ] Add definitions of LFH and STFHRichard Sandiford2013-09-301-0/+4
| | | | llvm-svn: 191661
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