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* [SystemZ] Add GRH32 for the high word of a GR64Richard Sandiford2013-09-306-14/+38
| | | | | | | | | The only thing this does on its own is make the definitions of RISB[HL]G a bit more precise. Those instructions are only used by the MC layer at the moment, so no behavioral change is intended. The class is needed by later patches though. llvm-svn: 191660
* [SystemZ] Rename subregs and add subreg_h32Richard Sandiford2013-09-309-60/+61
| | | | | | | | | | | | | Use subreg_hNN and subreg_lNN for the high and low NN bits of a register. List the low registers first, so that subreg_l32 also means the low 32 bits of a 128-bit register. Floats are stored in the upper 32 bits of a 64-bit register, so they should use subreg_h32 rather than subreg_l32. No behavioral change intended. llvm-svn: 191659
* [SystemZ] Add change missing from previous commitRichard Sandiford2013-09-301-1/+1
| | | | llvm-svn: 191656
* [SystemZ] Rename 32-bit GPR registersRichard Sandiford2013-09-306-20/+20
| | | | | | | | I'm about to add support for high-word operations, so it seemed better for the low-word registers to have names like R0L rather than R0W. No behavioral change intended. llvm-svn: 191655
* Various x86 disassembler fixes.Craig Topper2013-09-303-47/+12
| | | | | | | | | | | Add VEX_LIG to scalar FMA4 instructions. Use VEX_LIG in some of the inheriting checks in disassembler table generator. Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts. Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set. Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases. Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms. llvm-svn: 191649
* Change type of XOP flag in code emitters to a bool. Remove a some unneeded ↵Craig Topper2013-09-292-14/+8
| | | | | | cases from switch. llvm-svn: 191632
* Add comments for XOPA map introduced with TBM instructions.aCraig Topper2013-09-292-2/+4
| | | | llvm-svn: 191630
* Even more spelling fixes for "instruction".Robert Wilhelm2013-09-288-12/+12
| | | | llvm-svn: 191611
* Fix spelling intruction -> instruction.Robert Wilhelm2013-09-282-3/+3
| | | | llvm-svn: 191610
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-283-44/+40
| | | | | | | | We were completely ignoring the unorder/ordered attributes of condition codes and also incorrectly lowering seto and setuo. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 191603
* SelectionDAG: Improve legalization of SELECT_CC with illegal condition codesTom Stellard2013-09-281-4/+12
| | | | | | | | | | | SelectionDAG will now attempt to inverse an illegal conditon in order to find a legal one and if that doesn't work, it will attempt to swap the operands using the inverted condition. There are no new test cases for this, but a nubmer of the existing R600 tests hit this path. llvm-svn: 191602
* SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()Tom Stellard2013-09-282-76/+58
| | | | | | | | | | | | This is useful for targets like R600, which only support GT, GE, NE, and EQ condition codes as it removes the need to handle unsupported condition codes in target specific code. There are no tests with this commit, but R600 has been updated to take advantage of this new feature, so its existing selectcc tests are now testing the swapped operands path. llvm-svn: 191601
* MipsMachineFunction.cpp: Add missing #include <raw_ostream.h>NAKAMURA Takumi2013-09-281-0/+1
| | | | llvm-svn: 191597
* [mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted outAkira Hatanaka2013-09-284-19/+33
| | | | | | | | | | | | | | | | | | | | | | | | | of loops. Previously, two consecutive calls to function "func" would result in the following sequence of instructions: 1. load $16, %got(func)($gp) // load address of lazy-binding stub. 2. move $25, $16 3. jalr $25 // jump to lazy-binding stub. 4. nop 5. move $25, $16 6. jalr $25 // jump to lazy-binding stub again. With this patch, the second call directly jumps to func's address, bypassing the lazy-binding resolution routine: 1. load $25, %got(func)($gp) // load address of lazy-binding stub. 2. jalr $25 // jump to lazy-binding stub. 3. nop 4. load $25, %got(func)($gp) // load resolved address of func. 5. jalr $25 // directly jump to func. llvm-svn: 191591
* [mips] Define a derived class of PseudoSourceValue that represents a GOT entryAkira Hatanaka2013-09-272-0/+106
| | | | | | resolved by lazy-binding. llvm-svn: 191578
* [mips] Rewrite MipsTargetLowering::getAddr functions as template functions.Akira Hatanaka2013-09-273-81/+135
| | | | | | No intended functionality change. llvm-svn: 191546
* Adding intrinsics to the llvm backend for TBM instruction set.Yunzhong Gao2013-09-275-0/+89
| | | | | | Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
* [SystemZ] Rein back the use of block operationsRichard Sandiford2013-09-272-22/+28
| | | | | | | | | | | | | | The backend tries to use block operations like MVC, NC, OC and XC for simple scalar operations. For correctness reasons, it rejects any case in which the regions might partially overlap. However, for performance reasons, it should also reject cases where the regions might be equal, since the instruction might then not use the fast path. This fixes a performance regression seen in bzip2. We may want to limit the optimisation even more in future, or even remove it entirely, but I'll try with this for now. llvm-svn: 191525
* [SystemZ] Improve handling of PC-relative addressesRichard Sandiford2013-09-275-59/+92
| | | | | | | | | | | | | | The backend previously folded offsets into PC-relative addresses whereever possible. That's the right thing to do when the address can be used directly in a PC-relative memory reference (using things like LRL). But if we have a register-based memory reference and need to load the PC-relative address separately, it's better to use an anchor point that could be shared with other accesses to the same area of the variable. Fixes a FIXME. llvm-svn: 191524
* [mips][msa] Implemented insert.d intrinsic.Daniel Sanders2013-09-271-14/+3
| | | | | | | This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is further lowered into a sequence of insert.w's on MIPS32. llvm-svn: 191521
* ARM: Teach assembler to enforce constraints for ARM LDRD destination ↵Tilmann Scheller2013-09-271-1/+10
| | | | | | | | | | | | | | | | | | | register operands. As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints: LDRD<c> <Rt>, <Rt2>, ... (a) Rt must be even-numbered and not r14 (b) Rt2 must be R(t+1) If those two constraints are not met the result of executing the instruction will be unpredictable. Constraint (b) was already enforced, this commit adds support for constraint (a). Fixes rdar://14479793. llvm-svn: 191520
* [mips][msa] Implemented fill.d intrinsic.Daniel Sanders2013-09-271-3/+5
| | | | | | | This intrinsic is lowered into an equivalent BUILD_VECTOR which is further lowered into a sequence of insert.w's on MIPS32. llvm-svn: 191519
* [mips][msa] Implemented copy_[us].d intrinsic.Daniel Sanders2013-09-272-0/+21
| | | | | | | This intrinsic is lowered into equivalent copy_s.w instructions during legalization. llvm-svn: 191518
* [mips][msa] Rename arguments to MSA_INSERT_DESC_BASE to better match their ↵Daniel Sanders2013-09-271-6/+6
| | | | | | | | expected values. No functional change. llvm-svn: 191517
* [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.Daniel Sanders2013-09-273-0/+85
| | | | | | | For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. llvm-svn: 191515
* [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64Daniel Sanders2013-09-273-4/+104
| | | | | | | For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. llvm-svn: 191514
* [mips][msa] Added support for MSA registers to copyPhysRegDaniel Sanders2013-09-271-0/+4
| | | | llvm-svn: 191512
* [mips][msa] Added support for matching splati from normal IR (i.e. not ↵Daniel Sanders2013-09-279-8/+93
| | | | | | | | intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
* [mips][msa] Added MSA.txt to describe instruction selection quirks.Daniel Sanders2013-09-271-0/+30
| | | | | | | | This file contains notes about the instruction selection for MSA. For example, it notes that ilvl.d is cannot be selected because ilvev.d covers the same cases and is selected instead of ilvl.d. llvm-svn: 191507
* Fix comment.Tilmann Scheller2013-09-271-1/+1
| | | | llvm-svn: 191505
* ARM: Teach assembler to enforce constraint for Thumb2 LDRD ↵Tilmann Scheller2013-09-271-0/+11
| | | | | | | | | | | | | | | | | (literal/immediate) destination register operands. LDRD<c> <Rt>, <Rt2>, <label> LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}] LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm> LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]! As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2. If this constraint is not met the result of executing the instruction will be unpredictable. Fixes rdar://14479780. llvm-svn: 191504
* [mips][msa] Tidy upDaniel Sanders2013-09-271-131/+119
| | | | | | | | | | | | lowerMSABinaryIntr, lowerMSABinaryImmIntr, lowerMSABranchIntr, and lowerMSAUnaryIntr were trivially small functions. Inlined them into their callers. lowerMSASplat now takes its callers SDLoc instead of making a new one. No functional change. llvm-svn: 191503
* [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal ↵Daniel Sanders2013-09-271-0/+5
| | | | | | error when using it in FR=0 mode. llvm-svn: 191498
* [mips][msa] Expand all truncstores and loadexts for MSA as well as DSPDaniel Sanders2013-09-271-14/+16
| | | | llvm-svn: 191496
* [mips][msa] Added missing check in performSRACombineDaniel Sanders2013-09-271-0/+4
| | | | | | | | | | Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D1755 llvm-svn: 191495
* Put HasAVX512 predicate on some patterns to properly disable them when ↵Craig Topper2013-09-271-9/+11
| | | | | | AVX512 isn't enabled. Currently it works simply because the SSE and AVX version of the same patterns are checked first in the DAG isel table. llvm-svn: 191490
* Switch HasAVX to UseAVX in one spot to ensure that AVX512 form of VINSERTPS ↵Craig Topper2013-09-271-1/+1
| | | | | | is used in AVX512 mode. llvm-svn: 191489
* Removal some duplicate patterns.Craig Topper2013-09-271-8/+0
| | | | llvm-svn: 191488
* Fixing Intel format of the vshufpd instruction.Yunzhong Gao2013-09-271-2/+2
| | | | | | Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759 llvm-svn: 191481
* [mips][msa] Direct Object Emission for 3RF instructions.Jack Carter2013-09-262-112/+124
| | | | | | Patch by Matheus Almeida llvm-svn: 191461
* [mips][msa] Updates encoding of 3RF instructions to match the latest ↵Jack Carter2013-09-261-2/+2
| | | | | | | | | | revision of the MSA spec (1.06). This does not affect any of the existing output. Patch by Matheus Almeida llvm-svn: 191460
* Fix PR 17372: Emitting PLD for stack address for ARM Thumb2Weiming Zhao2013-09-261-0/+7
| | | | | | | t2PLDi12, t2PLDi8, t2PLDs was omitted in Thumb2InstrInfo. This patch fixes it. llvm-svn: 191441
* [PowerPC] Fix PR17354: Generate nop after local calls for PIC code.Bill Schmidt2013-09-261-1/+3
| | | | | | | | When generating code for shared libraries, even local calls may be intercepted, so we need a nop after the call for the linker to fix up the TOC. Test case adapted from the one provided in PR17354. llvm-svn: 191440
* [Sparc] Implements exception handling in SPARC with DwarfCFI.Venkatraman Govindaraju2013-09-263-4/+23
| | | | llvm-svn: 191432
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-266-305/+495
| | | | | | Patch by Artyom Skrobov. llvm-svn: 191428
* PPC: Allow partial fills in writeNopData()David Majnemer2013-09-261-4/+7
| | | | | | | | | | | | | | | | | | When asked to pad an irregular number of bytes, we should fill with zeros. This is consistent with the behavior specified in the AIX Assembler Language Reference as well as other LLVM and binutils assemblers. N.B. There is a small deviation from binutils' PPC assembler: when handling pads which are greater than 4 bytes but not mod 4, binutils will not emit any NOP sequences at all and only use zeros. This may or may not be a bug but there is no excellent rationale as to why that behavior is important to emulate. If that behavior is needed, we can change writeNopData() to behave in the same way. This fixes PR17352. llvm-svn: 191426
* Added temp flag -misched-bench for staging in default changes.Andrew Trick2013-09-261-1/+16
| | | | llvm-svn: 191423
* PPC: Do not introduce ISD nodes for fctid and fctiwDavid Majnemer2013-09-263-8/+6
| | | | llvm-svn: 191421
* PPC: Add support for fctid and fctiwDavid Majnemer2013-09-263-4/+12
| | | | | | | | | Encodings were checked against the Power ISA documents and double checked against binutils. This fixes PR17350. llvm-svn: 191419
* [mips][msa] Direct Object Emission for 3R instructions.Jack Carter2013-09-263-330/+402
| | | | | | | | This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
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