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* add the missing aliases for fp stack cmovs, rdar://8456391Chris Lattner2010-09-221-0/+6
| | | | llvm-svn: 114531
* reimplement elf TLS support in terms of addressing modes, eliminating ↵Chris Lattner2010-09-224-58/+42
| | | | | | SegmentBaseAddress. llvm-svn: 114529
* Fix rdar://8456364 - llvm-mc rejects '%CS'Chris Lattner2010-09-221-8/+13
| | | | llvm-svn: 114528
* fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp'Chris Lattner2010-09-221-0/+8
| | | | | | | | | -This line, and those below, will be ignored-- M test/MC/AsmParser/X86/x86_instructions.s M lib/Target/X86/AsmParser/X86AsmParser.cpp llvm-svn: 114527
* fix rdar://8456361 - llvm-mc rejects 'rep movsd'Chris Lattner2010-09-221-0/+6
| | | | llvm-svn: 114526
* convert the last 4 X86ISD nodes that should have memoperands to have them.Chris Lattner2010-09-224-41/+69
| | | | llvm-svn: 114523
* give X86ISD::FNSTCW16m a memoperand, since it touches memory. It onlyChris Lattner2010-09-223-16/+21
| | | | | | can access the stack due to how it is generated though. llvm-svn: 114522
* give FP_TO_INT16_IN_MEM and friends a memoperand. They are onlyChris Lattner2010-09-224-22/+29
| | | | | | used with stack slots, but hey, lets be safe. llvm-svn: 114521
* give VZEXT_LOAD a memory operand, it now works with segment registers.Chris Lattner2010-09-225-13/+14
| | | | llvm-svn: 114515
* revert r114386 now that address modes work correctly, we get a niceChris Lattner2010-09-221-4/+0
| | | | | | call through gs-relative memory now. llvm-svn: 114510
* give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace ↵Chris Lattner2010-09-213-10/+11
| | | | | | 256/257 llvm-svn: 114508
* OptimizeCompareInstr should avoid iterating pass the beginning of the MBB ↵Evan Cheng2010-09-211-1/+6
| | | | | | when the 'and' instruction is after the comparison. llvm-svn: 114506
* Add start of support for MC instruction printer of ARM jump tables. Filling inJim Grosbach2010-09-212-0/+74
| | | | | | the rest of it is next up. llvm-svn: 114500
* Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that ↵Owen Anderson2010-09-211-4/+0
| | | | | | | | this makes irrelevant, but add a new test for the new, improved functionality. llvm-svn: 114494
* reimplement support for GS and FS relative address space matchingChris Lattner2010-09-213-57/+44
| | | | | | | | | | | | | | | | | by having X86DAGToDAGISel::SelectAddr get passed in the parent node of the operand match (the load/store/atomic op) and having it get the address space from that, instead of having special FS/GS addr mode operations that require duplicating the entire instruction set to support. This makes FS and GS relative accesses *far* more predictable and work much better. It also simplifies the X86 backend a bit, more to come. There is still a pending issue with nodes like ISD::PREFETCH and X86ISD::FLD, which really should be MemSDNode's but aren't. llvm-svn: 114491
* Reimplement r114460 in target-independent DAGCombine rather than ↵Owen Anderson2010-09-212-23/+15
| | | | | | | | | target-dependent, by using the predicate to discover the number of sign bits. Enhance X86's target lowering to provide a useful response to this query. llvm-svn: 114473
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-2116-139/+126
| | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
* even though I'm about to rip it out, simplify the address mode stuffChris Lattner2010-09-212-28/+13
| | | | llvm-svn: 114468
* convert a couple more places to use the new getStore()Chris Lattner2010-09-212-11/+12
| | | | llvm-svn: 114463
* update a bunch of code to use the MachinePointerInfo version of getStore.Chris Lattner2010-09-219-59/+62
| | | | llvm-svn: 114461
* When adding the carry bit to another value on X86, exploit the fact that the ↵Owen Anderson2010-09-211-0/+23
| | | | | | | | | | | carry-materialization (sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold the intermediate AND and the ADD into a single SUB. This fixes <rdar://problem/8449754>. llvm-svn: 114460
* Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON loadBob Wilson2010-09-212-0/+64
| | | | | | and store intrinsics are represented with MemIntrinsicSDNodes. llvm-svn: 114454
* eliminate some uses of the getStore overload.Chris Lattner2010-09-213-41/+60
| | | | llvm-svn: 114453
* eliminate an old SelectionDAG::getTruncStore method, propagatingChris Lattner2010-09-213-10/+14
| | | | | | MachinePointerInfo around more. llvm-svn: 114452
* propagate MachinePointerInfo through various uses of the oldChris Lattner2010-09-215-36/+38
| | | | | | SelectionDAG::getExtLoad overload, and eliminate it. llvm-svn: 114446
* Fix errant printing of [v]ldm instructions that aren't a popJim Grosbach2010-09-211-32/+24
| | | | llvm-svn: 114445
* Fix buglet when the TST instruction directly uses the AND result.Gabor Greif2010-09-211-5/+6
| | | | | | | I am unable to write a test for this case, help is solicited, though... What I did is to tickle the code in the debugger and verify that we do the right thing. llvm-svn: 114430
* Move the search for the appropriate AND instructionGabor Greif2010-09-212-20/+44
| | | | | | | | | | into OptimizeCompareInstr. This necessitates the passing of CmpValue around, so widen the virtual functions to accomodate. No functionality changes. llvm-svn: 114428
* convert the targets off the non-MachinePointerInfo of getLoad.Chris Lattner2010-09-2111-102/+116
| | | | llvm-svn: 114410
* it's more elegant to put the "getConstantPool" andChris Lattner2010-09-214-29/+28
| | | | | | | | "getFixedStack" on the MachinePointerInfo class. While this isn't the problem I'm setting out to solve, it is the right way to eliminate PseudoSourceValue, so lets go with it. llvm-svn: 114406
* update the X86 backend to use the MachinePointerInfo version of oneChris Lattner2010-09-211-38/+44
| | | | | | | of the getLoad methods. This fixes at least one bug where an incorrect svoffset is passed in (a potential combiner-aa miscompile). llvm-svn: 114404
* Fix a bug where the x86 backend would lower memcpy/memset of segment ↵Chris Lattner2010-09-211-0/+9
| | | | | | | | relative operations into non-segment-relative copies. llvm-svn: 114402
* reimplement memcpy/memmove/memset lowering to use MachinePointerInfoChris Lattner2010-09-218-37/+31
| | | | | | | instead of srcvalue/offset pairs. This corrects SV info for mem operations whose size is > 32-bits. llvm-svn: 114401
* convert targets to the new MF.getMachineMemOperand interface.Chris Lattner2010-09-219-30/+42
| | | | llvm-svn: 114391
* fix rdar://8453210, a crash handling a call through a GS relative load.Chris Lattner2010-09-211-1/+7
| | | | | | For now, just disable folding the load into the call. llvm-svn: 114386
* Simplify ARM callee-saved register handling by removing the distinctionJim Grosbach2010-09-203-167/+59
| | | | | | | | | | | | | | | | | | | between the high and low registers for prologue/epilogue code. This was a Darwin-only thing that wasn't providing a realistic benefit anymore. Combining the save areas simplifies the compiler code and results in better ARM/Thumb2 codegen. For example, previously we would generate code like: push {r4, r5, r6, r7, lr} add r7, sp, #12 stmdb sp!, {r8, r10, r11} With this change, we combine the register saves and generate: push {r4, r5, r6, r7, r8, r10, r11, lr} add r7, sp, #12 rdar://8445635 llvm-svn: 114340
* idiom recognition should catch this.Chris Lattner2010-09-191-0/+32
| | | | llvm-svn: 114304
* add a readme.Chris Lattner2010-09-191-0/+25
| | | | llvm-svn: 114303
* X86Subtarget.h: Fix Cygwin's TD.NAKAMURA Takumi2010-09-181-1/+1
| | | | llvm-svn: 114297
* Add the exit instruction to the PTX target.Eric Christopher2010-09-1822-16/+705
| | | | | | Patch by Che-Liang Chiou <clchiou@gmail.com>! llvm-svn: 114294
* Fix build.Michael J. Spencer2010-09-181-0/+1
| | | | llvm-svn: 114292
* Thumb opcodes for thumb calls.Eric Christopher2010-09-181-1/+5
| | | | llvm-svn: 114263
* Add addrmode5 fp load support. Swap float/thumb operand adding to handleEric Christopher2010-09-181-5/+21
| | | | | | thumb with floating point. llvm-svn: 114256
* Floating point stores have a 3rd addressing mode type.Eric Christopher2010-09-181-1/+9
| | | | llvm-svn: 114254
* factor out a simple helper function to create a label for PC-relativeJim Grosbach2010-09-181-19/+17
| | | | | | instructions (PICADD, PICLDR, et.al.) llvm-svn: 114243
* PC-relative pseudo instructions are lowered and printed directly. Any encounterJim Grosbach2010-09-181-3/+2
| | | | | | with one in the generic printing code is an error. llvm-svn: 114242
* Fix vmov.f64 disassembly on targets where sizeof(long) != 8.Benjamin Kramer2010-09-171-2/+2
| | | | llvm-svn: 114240
* Add MC-inst handling for tPICADDJim Grosbach2010-09-171-0/+26
| | | | llvm-svn: 114237
* Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64Bob Wilson2010-09-171-0/+27
| | | | | | | | value should be in GPRs when it's going to be used as a scalar, and we use VMOVRRD to make that happen, but if the value is converted back to a vector we need to fold to a simple bit_convert. Radar 8407927. llvm-svn: 114233
* Teach the (non-MC) instruction printer to use the cannonical names for push/pop,Jim Grosbach2010-09-172-4/+72
| | | | | | and shift instructions on ARM. Update the tests to match. llvm-svn: 114230
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