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* This code implements most of mips16 hardfloat as it is done by gcc.Reed Kotler2012-12-152-0/+46
| | | | | | | | | | | | | | | | In this case, essentially it is soft float with different library routines. The next step will be to make this fully interoperational with mips32 floating point and that requires creating stubs for functions with signatures that contain floating point types. I have a more sophisticated design for mips16 hardfloat which I hope to implement at a later time that directly does floating point without the need for function calls. The mips16 encoding has no floating point instructions so one needs to switch to mips32 mode to execute floating point instructions. llvm-svn: 170259
* Make sure the alternate PC+imm syntax of LDR instruction with a smallKevin Enderby2012-12-141-1/+6
| | | | | | | | immediate generates the narrow version. Needed when doing round-trip assemble/disassemble testing using the alternate syntax that specifies 'pc' directly. llvm-svn: 170255
* TypeLegalizer: Do not generate target specific nodes with illegal types, ↵Nadav Rotem2012-12-141-0/+3
| | | | | | because we cant type-legalize them. llvm-svn: 170245
* This patch removes some nondeterminism from direct object file outputBill Schmidt2012-12-141-0/+45
| | | | | | | | | | for TLS dynamic models on 64-bit PowerPC ELF. The default sort routine for relocations only sorts on the r_offset field; but with TLS, there can be two relocations with the same r_offset. For PowerPC, this patch sorts secondarily on descending r_type, which matches the behavior expected by the linker. llvm-svn: 170237
* This patch improves the 64-bit PowerPC InitialExec TLS support by providingBill Schmidt2012-12-148-42/+53
| | | | | | | | | | | | | | | | | | | | | | | for a wider range of GOT entries that can hold thread-relative offsets. This matches the behavior of GCC, which was not documented in the PPC64 TLS ABI. The ABI will be updated with the new code sequence. Former sequence: ld 9,x@got@tprel(2) add 9,9,x@tls New sequence: addis 9,2,x@got@tprel@ha ld 9,x@got@tprel@l(9) add 9,9,x@tls Note that a linker optimization exists to transform the new sequence into the shorter sequence when appropriate, by replacing the addis with a nop and modifying the base register and relocation type of the ld. llvm-svn: 170209
* Remove two popcount patterns which we are already able to recognize.Shuxin Yang2012-12-131-15/+0
| | | | llvm-svn: 170158
* This is another cleanup patch for 64-bit PowerPC TLS processing. I hadBill Schmidt2012-12-133-57/+11
| | | | | | | some hackery in place that hid my poor use of TblGen, which I've now sorted out and cleaned up. No change in observable behavior, so no new test cases. llvm-svn: 170149
* Fix warnings with -DNDEBUGTom Stellard2012-12-133-2/+3
| | | | | | Patch by: NAKAMURA Takumi llvm-svn: 170142
* This is just a clean-up patch that simplifies the initial-exec TLS logic byBill Schmidt2012-12-134-19/+7
| | | | | | | avoiding use of machine operand flags. No change in observable behavior, so no new test cases. llvm-svn: 170141
* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-134-46/+40
| | | | | | | | | | | | Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. This is the second attempt. In the first attempt (r169837), a few getSimpleVT() were hoisted too far, detected by bootstrap failures. llvm-svn: 170104
* [mips] Do not copy GOT address to register $gp if the function being called hasAkira Hatanaka2012-12-131-4/+9
| | | | | | internal linkage. llvm-svn: 170092
* Add a way of printing out an arbitrary label name for a sectionEric Christopher2012-12-131-0/+2
| | | | | | given the section. llvm-svn: 170087
* [mips] Delete all floating point instruction classes that are no longer used.Akira Hatanaka2012-12-133-279/+2
| | | | | | No functionality change. llvm-svn: 170084
* [mips] Modify definitions of floating point conditional move instructions.Akira Hatanaka2012-12-132-24/+110
| | | | | | No functionality change. llvm-svn: 170080
* [mips] Modify definitions of floating point comparison instructions.Akira Hatanaka2012-12-132-9/+30
| | | | | | No functionality change. llvm-svn: 170077
* [mips] Modify definitions of floating point branch instructions.Akira Hatanaka2012-12-132-2/+26
| | | | | | No functionality change. llvm-svn: 170076
* [mips] Modify definitions of floating point indexed load and store instructions.Akira Hatanaka2012-12-132-14/+59
| | | | | | No functionality change. llvm-svn: 170075
* [mips] Modify definitions of floating point multiply-add/sub instructions.Akira Hatanaka2012-12-132-12/+46
| | | | | | No functionality change. llvm-svn: 170073
* [mips] Modify definitions of floating point load and store instructions.Akira Hatanaka2012-12-132-10/+35
| | | | | | No functionality change. llvm-svn: 170072
* [mips] Modify definitions of move from/to coprocessor instructions.Akira Hatanaka2012-12-132-21/+30
| | | | | | No functionality change. llvm-svn: 170071
* [mips] Modify definitions of two register operand floating point instructions.Akira Hatanaka2012-12-132-41/+87
| | | | | | No functionality change. llvm-svn: 170069
* [mips] Modify definitions of three register operand floating point instructionsAkira Hatanaka2012-12-132-8/+41
| | | | | | and separate encoding information from the rest. llvm-svn: 170066
* Avoid setIsInsideBundle in Target/R600.Jakob Stoklund Olesen2012-12-132-10/+11
| | | | | | This function is going to be removed. llvm-svn: 170064
* [mips] Move classes that do not belong in MipsInstrFormats.td intoAkira Hatanaka2012-12-132-23/+23
| | | | | | | MipsInstrFPU.td. llvm-svn: 170061
* [mips] Set isCommutable flag in a more explicit way.Akira Hatanaka2012-12-131-5/+3
| | | | llvm-svn: 170060
* [mips] Remove fmt from the parameter list of classes FMADDSUB and FNMADDSUB.Akira Hatanaka2012-12-131-16/+16
| | | | llvm-svn: 170057
* [mips] Remove single-precision floating point instruction from multiclassAkira Hatanaka2012-12-132-10/+13
| | | | | | | FFR2P_M. llvm-svn: 170055
* [mips] Move class IsCommutable into MipsInstrInfo.td.Akira Hatanaka2012-12-132-4/+4
| | | | llvm-svn: 170054
* [mips] Remove single-precision floating point instructions from multiclassesAkira Hatanaka2012-12-132-47/+54
| | | | | | | | FFR1_W_M and FFR1P_M. The new instruction definitions have one-to-one correspondence with the instructions in the ISA manual. llvm-svn: 170053
* Fix a bogus commentEli Bendersky2012-12-131-3/+3
| | | | llvm-svn: 170052
* [mips] Fix a memory leak bug report by NAKAMURA Takumi.Akira Hatanaka2012-12-121-5/+6
| | | | llvm-svn: 170012
* This patch implements local-dynamic TLS model support for the 64-bitBill Schmidt2012-12-1210-18/+242
| | | | | | | | | | | | | | | | | | | | | | PowerPC target. This is the last of the four models, so we now have full TLS support. This is mostly a straightforward extension of the general dynamic model. I had to use an additional Chain operand to tie ADDIS_DTPREL_HA to the register copy following ADDI_TLSLD_L; otherwise everything above the ADDIS_DTPREL_HA appeared dead and was removed. As before, there are new test cases to test the assembly generation, and the relocations output during integrated assembly. The expected code gen sequence can be read in test/CodeGen/PowerPC/tls-ld.ll. There are a couple of things I think can be done more efficiently in the overall TLS code, so there will likely be a clean-up patch forthcoming; but for now I want to be sure the functionality is in place. Bill llvm-svn: 170003
* Add ARM NONE and PREL31 relocation types.Logan Chien2012-12-121-1/+8
| | | | | | | | Add R_ARM_NONE and R_ARM_PREL31 relocation types to MCExpr. Both of them will be used while generating .ARM.extab and .ARM.exidx sections. llvm-svn: 169965
* [CMake] Fixup R600.NAKAMURA Takumi2012-12-121-1/+1
| | | | llvm-svn: 169962
* Sorry about the churn. One more change to getOptimalMemOpType() hook. Did IEvan Cheng2012-12-128-32/+30
| | | | | | | | | | | | mention the inline memcpy / memset expansion code is a mess? This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset. The first indicates whether it is expanding a memset or a memcpy / memmove. The later is whether the memset is a memset of zero. It's totally possible (likely even) that targets may want to do different things for memcpy and memset of zero. llvm-svn: 169959
* - Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.Evan Cheng2012-12-128-31/+21
| | | | | | | | | Also added more comments to explain why it is generally ok to return true. - Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to be true for loaded source (memcpy) or zero constants (memset). The poor name choice is probably some kind of legacy issue. llvm-svn: 169954
* Avoid using lossy load / stores for memcpy / memset expansion. e.g.Evan Cheng2012-12-124-0/+26
| | | | | | f64 load / store on non-SSE2 x86 targets. llvm-svn: 169944
* Trim unneeded header #include.Jim Grosbach2012-12-111-1/+0
| | | | llvm-svn: 169933
* ARM: Remove old testing option.Jim Grosbach2012-12-111-5/+1
| | | | | | | Pre-regalloc frame allocation and referencing has been on by default for ages. No need for the testing option that disables it. llvm-svn: 169931
* ARM: Remove old testing options.Jim Grosbach2012-12-111-13/+0
| | | | | | Base pointer referencing has been enabled for ages. llvm-svn: 169930
* Replace TargetLowering::isIntImmLegal() withEvan Cheng2012-12-113-22/+46
| | | | | | | | | ScalarTargetTransformInfo::getIntImmCost() instead. "Legal" is a poorly defined term for something like integer immediate materialization. It is always possible to materialize an integer immediate. Whether to use it for memcpy expansion is more a "cost" conceern. llvm-svn: 169929
* Add R600 backendTom Stellard2012-12-11105-1/+19559
| | | | | | A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
* This patch implements the general dynamic TLS model for 64-bit PowerPC.Bill Schmidt2012-12-1110-14/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Given a thread-local symbol x with global-dynamic access, the generated code to obtain x's address is: Instruction Relocation Symbol addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x R_PPC64_REL24 __tls_get_addr nop <use address in r3> The implementation borrows from the medium code model work for introducing special forms of ADDIS and ADDI into the DAG representation. This is made slightly more complicated by having to introduce a call to the external function __tls_get_addr. Using the full call machinery is overkill and, more importantly, makes it difficult to add a special relocation. So I've introduced another opcode GET_TLS_ADDR to represent the function call, and surrounded it with register copies to set up the parameter and return value. Most of the code is pretty straightforward. I ran into one peculiarity when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like BL8_NOP_ELF except that it takes another parameter to represent the symbol ("x" above) that requires a relocation on the call. Something in the TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated identically during the emit phase, so this second operand was never visited to generate relocations. This is the reason for the slightly messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding(). Two new tests are included to demonstrate correct external assembly and correct generation of relocations using the integrated assembler. Comments welcome! Thanks, Bill llvm-svn: 169910
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-117-53/+59
| | | | llvm-svn: 169854
* Change TargetLowering::getTypeForExtArgOrReturn to take and returnPatrik Hagglund2012-12-112-5/+5
| | | | | | | | MVTs, instead of EVTs. Accordingly, add bitsLT (and similar) to MVT. llvm-svn: 169850
* Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund2012-12-111-2/+2
| | | | | | EVTs. llvm-svn: 169848
* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-114-6/+6
| | | | | | of EVT. llvm-svn: 169845
* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-114-46/+40
| | | | | | | | | Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. llvm-svn: 169837
* [CMake] Remove dependencies to intrinsics_gen I introduced in r169724.NAKAMURA Takumi2012-12-113-3/+3
| | | | llvm-svn: 169819
* Use multiclass for new-value store instructions with MEMri operand.Jyotsna Verma2012-12-111-148/+46
| | | | llvm-svn: 169814
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