summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* Define and handle additional fixup kinds. By Adhemerval Zanella.Roman Divacky2012-08-162-1/+20
| | | | llvm-svn: 162037
* Fix typo and grammar. By Adhemerval Zanella.Roman Divacky2012-08-161-1/+1
| | | | llvm-svn: 162032
* [arm-fast-isel] Add support for fastcc.Jush Lu2012-08-161-3/+6
| | | | | | | | Without fastcc support, the caller just falls through to CallingConv::C for fastcc, but callee still uses fastcc, this inconsistency of calling convention is a problem, and fastcc support can fix it. llvm-svn: 162013
* Patch to enable FMA on bdver2 target. Make XOP feature enable FMA4 as well.Anitha Boyapati2012-08-161-2/+2
| | | | llvm-svn: 162012
* (no commit message)Anitha Boyapati2012-08-161-2/+2
| | | | llvm-svn: 162010
* Add Android ABI to Mips backend to handle functions returning vectors of fourAkira Hatanaka2012-08-163-0/+18
| | | | | | floats. llvm-svn: 162008
* Fold predicable instructions into MOVCC / t2MOVCC.Jakob Stoklund Olesen2012-08-155-2/+104
| | | | | | | | | | | | | | The ARM select instructions are just predicated moves. If the select is the only use of an operand, the instruction defining the operand can be predicated instead, saving one instruction and decreasing register pressure. This implementation can turn AND/ORR/EOR instructions into their corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to predicate any instruction, but we don't yet support predicated instructions in SSA form. llvm-svn: 161994
* Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows ↵Evan Cheng2012-08-154-2/+50
| | | | | | unaligned access. rdar://12091029 llvm-svn: 161962
* Add missing Rfalse operand to the predicated pseudo-instructions.Jakob Stoklund Olesen2012-08-153-28/+41
| | | | | | | | | | | | | | | | | | | | | | | When predicating this instruction: Rd = ADD Rn, Rm We need an extra operand to represent the value given to Rd when the predicate is false: Rd = ADDCC Rfalse, Rn, Rm, pred The Rd and Rfalse operands are different registers while in SSA form. Rfalse is tied to Rd to make sure they get the same register during register allocation. Previously, Rd and Rn were tied, but that is not required. Compare to MOVCC: Rd = MOVCC Rfalse, Rtrue, pred llvm-svn: 161955
* The names of VFP variants of half-to-float conversion instructions wereAnton Korobeynikov2012-08-141-7/+7
| | | | | | | | reversed. This leads to wrong codegen for float-to-half conversion intrinsics which are used to support storage-only fp16 type. NEON variants of same instructions are fine. llvm-svn: 161907
* This needs braces. Spotted by Bill.Eric Christopher2012-08-141-1/+2
| | | | llvm-svn: 161906
* minor fix of X86ISD::VSEXT_MOVL dumpMichael Liao2012-08-141-0/+1
| | | | llvm-svn: 161902
* fix PR11334Michael Liao2012-08-144-0/+99
| | | | | | | | | | | | - FP_EXTEND only support extending from vectors with matching elements. This results in the scalarization of extending to v2f64 from v2f32, which will be legalized to v4f32 not matching with v2f64. - add X86-specific VFPEXT supproting extending from v4f32 to v2f64. - add BUILD_VECTOR lowering helper to recover back the original extending from v4f32 to v2f64. - test case is enhanced to include different vector width. llvm-svn: 161894
* Switch the fixed-length disassembler to be table-driven.Jim Grosbach2012-08-142-419/+437
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
* Factor duplicate calls to getUNDEF in several functions.Craig Topper2012-08-141-10/+10
| | | | llvm-svn: 161860
* Re-factor intrinsic lowering to combine common parts of similar intrinsics. ↵Craig Topper2012-08-141-34/+133
| | | | | | Reduces compiled code size a little bit. llvm-svn: 161859
* Remove the TII::scheduleTwoAddrSource() hook.Jakob Stoklund Olesen2012-08-132-47/+0
| | | | | | | | | | | | | | | It never does anything when running 'make check', and it get's in the way of updating live intervals in 2-addr. The hook was originally added to help form IT blocks in Thumb2 code before register allocation, but the pass ordering has changed since then, and we run if-conversion after register allocation now. When the MI scheduler is enabled, there will be no less than two schedulers between 2-addr and Thumb2ITBlockPass, so this hook is unlikely to help anything. llvm-svn: 161794
* ARM: enable struct byval for AAPCS-VFP.Manman Ren2012-08-131-0/+3
| | | | | | | | This change is to be enabled in clang. rdar://9877866 llvm-svn: 161789
* [Hexagon] Don't mark callee saved registers as clobbered by a tail callArnold Schwaighofer2012-08-131-9/+3
| | | | | | | | | | This was causing unnecessary spills/restores of callee saved registers. Fixes PR13572. Patch by Pranav Bhandarkar! llvm-svn: 161778
* Do not optimize (or (and X,Y), Z) into BFI and other sequences if the AND ↵Nadav Rotem2012-08-131-1/+5
| | | | | | | | ISDNode has more than one user. rdar://11876519 llvm-svn: 161775
* X86: move Int_CVTSD2SSrr, Int_CVTSI2SSrr, Int_CVTSI2SDrr, Int_CVTSS2SDrr fromManman Ren2012-08-131-6/+6
| | | | | | | | | OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be changed to a memory operand. PR13576 llvm-svn: 161769
* Add support for the %H output modifier.Eric Christopher2012-08-131-2/+15
| | | | | | Patch by Weiming Zhao. llvm-svn: 161768
* X86: when auto-detecting the subtarget features, make sure use IsIntel to detectManman Ren2012-08-131-2/+2
| | | | | | Nehalem, Westmere and Sandy Bridge. AMD also has processor family 6. llvm-svn: 161763
* Use correct loads for vector types during extending-load operations.Tim Northover2012-08-131-36/+36
| | | | | | | | Previously, we used VLD1.32 in all cases, however there are both 16 and 64-bit accesses being selected, so we need to use an appropriate width load in those cases. llvm-svn: 161748
* Tidy up VSETCC lowering code a bit more by adding an llvm_unreachable and ↵Craig Topper2012-08-131-7/+9
| | | | | | putting an a couple if conditions in a better order. llvm-svn: 161746
* Refactor code a bit to share commonalities. No functional change intended.Craig Topper2012-08-131-20/+21
| | | | llvm-svn: 161745
* Fix an unused variable warning from r161742.Craig Topper2012-08-131-3/+0
| | | | llvm-svn: 161743
* Remove the LowerMMXCONCAT_VECTORS function. It could never execute because ↵Craig Topper2012-08-133-57/+1
| | | | | | there are no legal 64-bit vector types that could be used as inputs to a 128-bit concat_vectors. Remove a target specific SDNode and its patterns that become unused as a result. llvm-svn: 161742
* Remove call to setOperationAction for SETCC of v4f32. SETCC returns an ↵Craig Topper2012-08-121-1/+0
| | | | | | integer type not an FP type. llvm-svn: 161738
* Remove unnecessary call to setOperationAction for SETCC of v2i64 under ↵Craig Topper2012-08-121-3/+0
| | | | | | SSE42. It was already called for the same under SSE2. llvm-svn: 161737
* Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARMArnold Schwaighofer2012-08-125-251/+17
| | | | | | | | | architecture It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7 thumb O3. llvm-svn: 161736
* Change addTypeForNeon to use MVT instead of EVT so all the calls to ↵Craig Topper2012-08-122-51/+46
| | | | | | getSimpleVT can be removed. llvm-svn: 161735
* Make replace many calls to getSizeInBits() with is128BitVector/is256BitVectorCraig Topper2012-08-121-60/+65
| | | | llvm-svn: 161734
* Use MVT.isXBitVector instead of EVT.isXBitVector when setting up operation ↵Craig Topper2012-08-121-41/+35
| | | | | | actions. Compiles to smaller code. llvm-svn: 161733
* fix PR13577, an issue introduced by r161687Michael Liao2012-08-111-1/+19
| | | | | | | | - FCMOV only supports a subset of X86 conditions. Skip boolean simplification if X86 condition is not valid for FCMOV. - add a minimal test case for PR13577. llvm-svn: 161732
* Move setOperationAction for CONCAT_VECTORS for 256-bit vectors into loop ↵Craig Topper2012-08-111-7/+2
| | | | | | since all 256-bit types are supported. llvm-svn: 161730
* Tidy up indentation. No functional change.Craig Topper2012-08-111-25/+25
| | | | llvm-svn: 161727
* Fix a cast that was casting away 'const' unnecessarily Craig Topper2012-08-111-1/+1
| | | | llvm-svn: 161726
* Add a couple default: llvm_unreachable() to some switch statements. Fix a ↵Craig Topper2012-08-111-2/+4
| | | | | | bad message in an existing llvm_unreachable. llvm-svn: 161725
* X86: when we are auto-detecting the subtarget features, make sure we turn onManman Ren2012-08-101-2/+5
| | | | | | | | | | FeatureFastUAMem for Nehalem, Westmere and Sandy Bridge. FeatureFastUAMem is already on if we pass in nehalem or westmere as a command argument. rdar: 7252306 llvm-svn: 161717
* ARM: enable struct byval for AAPCS.Manman Ren2012-08-101-0/+3
| | | | | | | | | This change is to be enabled in clang. rdar://9877866 PR://13350 llvm-svn: 161693
* add X86-specific DAG optimization to simplify boolean testMichael Liao2012-08-101-4/+113
| | | | | | | | | | | | | - if a boolean test (X86ISD::CMP or X86ISD:SUB) checks a boolean value generated from X86ISD::SETCC, try to simplify the boolean value generation and checking by reusing the original EFLAGS with proper condition code - add hooks to X86 specific SETCC/BRCOND/CMOV, the major 3 places consuming EFLAGS part of patches fixing PR12312 llvm-svn: 161687
* remove tailing whitespaces and test commitMichael Liao2012-08-101-3/+3
| | | | llvm-svn: 161664
* Add some missing includes for the build against stdcxx.Joerg Sonnenberger2012-08-101-0/+1
| | | | llvm-svn: 161657
* Remove getARMRegisterNumbering and replace with calls intoEric Christopher2012-08-097-154/+90
| | | | | | | | | | | the register info for getEncodingValue. This builds on the small patch of yesterday to set HWEncoding in the register file. One (deprecated) use was turned into a hard number to avoid needing register info in the old JIT. llvm-svn: 161628
* Don't modify MO while use_iterator is still pointing to it.Jakob Stoklund Olesen2012-08-091-3/+4
| | | | llvm-svn: 161626
* [ms-inline asm] Extend the MC AsmParser API to match MCInsts (but not emit).Chad Rosier2012-08-091-3/+19
| | | | | | | | | | This new API will be used by clang to parse ms-style inline asms. One goal of this project is to use this style of inline asm for targets other then x86. Therefore, this API needs to be implemented for non-x86 targets at some point in the future. llvm-svn: 161624
* Another 32 to 64 bit sign extension bug.Jack Carter2012-08-091-1/+1
| | | | | | The fields in the td definition were switched. llvm-svn: 161607
* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-08-095-17/+251
| | | | | | | | | | | This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 161581
* This field isn't used anymore, use it with HWEncoding instead.Eric Christopher2012-08-091-4/+4
| | | | llvm-svn: 161564
OpenPOWER on IntegriCloud