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* Added storeRegToAddr, loadRegFromAddr, and unfoldMemoryOperand's.Evan Cheng2007-10-052-114/+331
| | | | llvm-svn: 42624
* Not needed any more.Evan Cheng2007-10-051-1/+0
| | | | llvm-svn: 42623
* Forgot these.Evan Cheng2007-10-052-0/+72
| | | | llvm-svn: 42622
* - Added a few target hooks to generate load / store instructions from / to anyEvan Cheng2007-10-0510-68/+460
| | | | | | | | address (not just from / to frameindexes). - Added target hooks to unfold load / store instructions / SDNodes into separate load, data processing, store instructions / SDNodes. llvm-svn: 42621
* add a note.Chris Lattner2007-10-041-0/+40
| | | | llvm-svn: 42607
* Use empty() member functions when that's what's being tested for insteadDan Gohman2007-10-036-12/+12
| | | | | | of comparing begin() and end(). llvm-svn: 42585
* add a noteChris Lattner2007-10-031-0/+32
| | | | llvm-svn: 42579
* add a noteChris Lattner2007-10-031-0/+16
| | | | llvm-svn: 42573
* Bill's example is still not enough to repro this, but it has other issues thatChris Lattner2007-10-031-0/+8
| | | | | | seem significant as well. llvm-svn: 42564
* Another micro-opt.Bill Wendling2007-10-021-0/+16
| | | | llvm-svn: 42554
* Another missed optimization with LICM.Bill Wendling2007-10-021-0/+23
| | | | llvm-svn: 42552
* Small label changes.Bill Wendling2007-10-021-5/+2
| | | | llvm-svn: 42549
* Now with source code.Bill Wendling2007-10-021-0/+16
| | | | llvm-svn: 42548
* Now with LL code!Bill Wendling2007-10-021-1/+17
| | | | llvm-svn: 42547
* Another missed optimization.Bill Wendling2007-10-021-0/+28
| | | | llvm-svn: 42546
* Micro-optimization -- missed LICM opportunity.Bill Wendling2007-10-021-0/+24
| | | | llvm-svn: 42542
* Rewrite sqrt and powi to use anyfloat. By popular demand.Dale Johannesen2007-10-021-4/+2
| | | | llvm-svn: 42537
* Refactor code to add load / store folded instructions -> register onlyEvan Cheng2007-10-012-607/+599
| | | | | | instructions reverse map. llvm-svn: 42509
* Typo. X86comi doesn't read / write chain's.Evan Cheng2007-10-011-2/+1
| | | | llvm-svn: 42492
* Add getABITypeSize, getABITypeSizeInBitsDale Johannesen2007-10-011-1/+6
| | | | llvm-svn: 42488
* AsmPrinters overriding getAnalysisUsage should call super.Gordon Henriksen2007-09-302-1/+2
| | | | | | And not super's super, either. llvm-svn: 42482
* Enabling new condition code modeling scheme.Evan Cheng2007-09-2910-1649/+308
| | | | llvm-svn: 42459
* Refactor the memcpy lowering for the x86 target.Rafael Espindola2007-09-282-56/+62
| | | | | | | | The only generated code difference is that now we call memcpy when the size of the array is unknown. This matches GCC behavior and is better since the run time value can be arbitrarily large. llvm-svn: 42433
* Stop inventing new words. :-)Evan Cheng2007-09-281-1/+1
| | | | llvm-svn: 42429
* Pessimisively assume ADJCALLSTACKDOWN / ADJCALLSTACKUP (which becomes sub / ↵Evan Cheng2007-09-281-1/+3
| | | | | | add) clobbers EFLAGS. llvm-svn: 42426
* TargetAsmInfo::getAddressSize() was incorrect for x86-64 and 64-bit targetsDan Gohman2007-09-273-4/+2
| | | | | | | | other than PPC64. Instead of fixing it, just remove it and fix all the places that use it to use TargetData::getPointerSize() instead, as there aren't very many. Most of the references were in DwarfWriter.cpp. llvm-svn: 42419
* Use GR64 in 64-bit mode.Evan Cheng2007-09-271-1/+4
| | | | llvm-svn: 42417
* Doh. Calls clobber EFLAGS.Evan Cheng2007-09-271-1/+1
| | | | llvm-svn: 42413
* Make temporaries explicit to avoid prematureDale Johannesen2007-09-261-1/+3
| | | | | | destruction of compiler-created ones. llvm-svn: 42383
* - Move getPhysicalRegisterRegClass() from ScheduleDAG to MRegisterInfo.Evan Cheng2007-09-261-0/+15
| | | | | | | - Added ability to emit cross class register copies to the BBRU scheduler. - More aggressive backtracking. llvm-svn: 42375
* - Added MRegisterInfo::getCrossCopyRegClass() hook. For register classes ↵Evan Cheng2007-09-262-0/+33
| | | | | | | | where reg to reg copies are not possible, this returns another register class which registers in the specified register class can be copied to (and copy back from). - X86 copyRegToReg() now supports copying between EFLAGS and GR32 / GR64 registers. llvm-svn: 42372
* Some assemblers do not recognize aliases pushfd, pushfq, popfd, and popfq. ↵Evan Cheng2007-09-262-4/+4
| | | | | | Just emit them as pushf and popf. llvm-svn: 42371
* Enable codegen for long double abs, sin, cosDale Johannesen2007-09-261-0/+4
| | | | llvm-svn: 42368
* Typos: POPQ -> POPFQ, POPD -> POPFD.Evan Cheng2007-09-262-2/+2
| | | | llvm-svn: 42348
* move PR1160 here.Chris Lattner2007-09-261-0/+31
| | | | llvm-svn: 42347
* Allow copyRegToReg to emit cross register classes copies.Evan Cheng2007-09-2614-44/+92
| | | | | | Tested with "make check"! llvm-svn: 42346
* move PR1264 here.Chris Lattner2007-09-261-1/+28
| | | | llvm-svn: 42345
* Add pushf{d|q}, popf{d|q} to push and pop EFLAGS register.Evan Cheng2007-09-262-4/+12
| | | | llvm-svn: 42335
* translateX86CC updates the last two operands.Evan Cheng2007-09-261-2/+5
| | | | llvm-svn: 42333
* Correctly restore stack pointer after realignment in main() on Cygwin/Mingw32Anton Korobeynikov2007-09-261-1/+8
| | | | llvm-svn: 42332
* Missing load / store folding entries.Evan Cheng2007-09-251-0/+8
| | | | llvm-svn: 42323
* Partly revert invalid r41774Anton Korobeynikov2007-09-251-0/+20
| | | | llvm-svn: 42322
* More explicit keywords.Dan Gohman2007-09-257-9/+9
| | | | llvm-svn: 42316
* Fix a typo in a comment.Dan Gohman2007-09-251-1/+1
| | | | llvm-svn: 42313
* New style x87 cmp instructions.Evan Cheng2007-09-252-0/+24
| | | | llvm-svn: 42312
* When both x/y and x%y are needed (x and y both scalar integer), computeDan Gohman2007-09-253-25/+88
| | | | | | | | | both results with a single div or idiv instruction. This uses new X86ISD nodes for DIV and IDIV which are introduced during the legalize phase so that the SelectionDAG's CSE can automatically eliminate redundant computations. llvm-svn: 42308
* Move the setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand) andDan Gohman2007-09-251-7/+1
| | | | | | | the check to see if the assembler supports .loc from X86TargetLowering into the superclass TargetLowering. llvm-svn: 42297
* Added support for new condition code modeling scheme (i.e. physical register ↵Evan Cheng2007-09-259-45/+1409
| | | | | | | | dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
* New temporary option -new-cc-modeling-scheme to test the new cc modeling scheme.Evan Cheng2007-09-251-0/+6
| | | | llvm-svn: 42283
* Rename keyword "modify" -> "implicit".Evan Cheng2007-09-251-1/+1
| | | | llvm-svn: 42282
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