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* R600/SI: Move more information into SIProgramInfo structTom Stellard2014-12-023-50/+80
| | | | llvm-svn: 223154
* [mips] Fix passing of small structures for big-endian O32.Daniel Sanders2014-12-021-0/+16
| | | | | | | | | | | | | | | | | | | Summary: Like N32/N64, they must be passed in the upper bits of the register. The new code could be merged with the existing if-statements but I've refrained from doing this since it will make porting the O32 implementation to tablegen harder later. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6463 llvm-svn: 223148
* Introduce CPUStringIsValid() into MCSubtargetInfo and use it for ARM .cpu ↵Roman Divacky2014-12-021-0/+11
| | | | | | | | | | parsing. Previously .cpu directive in ARM assembler didnt switch to the new CPU and therefore acted as a nop. This implemented real action for .cpu and eg. allows to assembler FreeBSD kernel with -integrated-as. llvm-svn: 223147
* R600/SI: Refactor AMDGPUAsmPrinter::EmitProgramInfoSI()Tom Stellard2014-12-021-9/+11
| | | | llvm-svn: 223144
* Remove unneccessary code introduced with 223101.Philip Reames2014-12-021-10/+2
| | | | llvm-svn: 223132
* R600/SI: Set correct number of user sgprs for HSA runtimeTom Stellard2014-12-021-1/+4
| | | | | | We don't support scratch buffers yet with HSA. llvm-svn: 223130
* fix typo in commentSanjay Patel2014-12-021-1/+1
| | | | llvm-svn: 223127
* AArch64: make register block rules apply to vector types too.Tim Northover2014-12-021-3/+3
| | | | | | | | The blocking code originated in ARM, which is more aggressive about casting types to a canonical representative before doing anything else, so I missed out most vector HFAs and broke the ABI. This should fix it. llvm-svn: 223126
* R600/SI: Set the ATC bit on all resource descriptors for the HSA runtimeTom Stellard2014-12-026-9/+33
| | | | llvm-svn: 223125
* Remove unused function.Asiri Rathnayake2014-12-022-12/+0
| | | | | | | | | Removing an unused function which is causing one of the build bots to fail. This was introduced in the commit r223113. A proper cleanup of the so_imm tblgen defintion (made redundant by the mod_imm definition) needs to happen soon. llvm-svn: 223115
* Add support for ARM modified-immediate assembly syntax.Asiri Rathnayake2014-12-026-35/+345
| | | | | | | | | | | | | | | | | | | | Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
* Emit Tag_ABI_FP_denormal correctly in fast-math mode.Charlie Turner2014-12-021-1/+26
| | | | | | | | | | | | | | | | | | | | The default ARM floating-point mode does not support IEEE 754 mode exactly. Of relevance to this patch is that input denormals are flushed to zero. The way in which they're flushed to zero depends on the architecture, * For VFPv2, it is implementation defined as to whether the sign of zero is preserved. * For VFPv3 and above, the sign of zero is always preserved when a denormal is flushed to zero. When FP support has been disabled, the strategy taken by this patch is to assume the software support will mirror the behaviour of the hardware support for the target *if it existed*. That is, for architectures which can only have VFPv2, it is assumed the software will flush to positive zero. For later architectures it is assumed the software will flush to zero preserving sign. Change-Id: Icc5928633ba222a4ba3ca8c0df44a440445865fd llvm-svn: 223110
* Fix variable used only in assertion.Nick Lewycky2014-12-021-1/+2
| | | | llvm-svn: 223101
* Try to fix a bot failure due to a variable used only in an assert.Philip Reames2014-12-011-4/+4
| | | | | | Specifically, bot lld-x86_64-darwin13. Resulting from change 223085. llvm-svn: 223092
* [Statepoints 2/4] Statepoint infrastructure for garbage collection: MI & ↵Philip Reames2014-12-014-1/+145
| | | | | | | | | | | | | | x86-64 Backend This is the second patch in a small series. This patch contains the MachineInstruction and x86-64 backend pieces required to lower Statepoints. It does not include the code to actually generate the STATEPOINT machine instruction and as a result, the entire patch is currently dead code. I will be submitting the SelectionDAG parts within the next 24-48 hours. Since those pieces are by far the most complicated, I wanted to minimize the size of that patch. That patch will include the tests which exercise the functionality in this patch. The entire series can be seen as one combined whole in http://reviews.llvm.org/D5683. The STATEPOINT psuedo node is generated after all gc values are explicitly spilled to stack slots. The purpose of this node is to wrap an actual call instruction while recording the spill locations of the meta arguments used for garbage collection and other purposes. The STATEPOINT is modeled as modifing all of those locations to prevent backend optimizations from forwarding the value from before the STATEPOINT to after the STATEPOINT. (Doing so would break relocation semantics for collectors which wish to relocate roots.) The implementation of STATEPOINT is closely modeled on PATCHPOINT. Eventually, much of the code in this patch will be removed. The long term plan is to merge the functionality provided by statepoints and patchpoints. Merging their implementations in the backend is likely to be a good starting point. Reviewed by: atrick, ributzka llvm-svn: 223085
* [NVPTX] Do not emit .weak symbols for NVPTXJingyue Wu2014-12-011-0/+1
| | | | | | | | | | | | | | | | | | | Summary: ".weak" symbols cannot be consumed by ptxas (PR21685). This patch makes the weak directive in MCAsmPrinter customizable, and disables emitting ".weak" symbols for NVPTX. Test Plan: weak-linkage.ll Reviewers: jholewinski Reviewed By: jholewinski Subscribers: majnemer, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D6455 llvm-svn: 223077
* [AArch64] Don't combine "select (setcc i1 LHS, RHS), vL, vR".Ahmed Bougacha2014-12-011-0/+6
| | | | | | | | | | | | | r208210 introduced an optimization that improves the vector select codegen by doing the setcc on vectors directly. This is a problem they the setcc operands are i1s, because the optimization would create vectors of i1, which aren't legal. Part of PR21549. Differential Revision: http://reviews.llvm.org/D6308 llvm-svn: 223075
* [AArch64] Fix v2i8->i16 bitcast legalization.Ahmed Bougacha2014-12-011-5/+4
| | | | | | | | | | | | | | | r213378 improved f16 bitcasts, so that they go directly through subregs, instead of through the stack. That code now causes an assertion failure for bitcasts from other 16-bits types (most importantly v2i8). Correct that by doing the custom lowering for i16 bitcasts only when the input is an f16. Part of PR21549. Differential Revision: http://reviews.llvm.org/D6307 llvm-svn: 223074
* ARM: lower tail calls correctly when using GHC calling convention.Tim Northover2014-12-012-38/+55
| | | | | | Patch by Ben Gamari. llvm-svn: 223055
* R600/SI: Various instruction format bit test cleanupsMatt Arsenault2014-12-015-94/+134
| | | | | | | | | | | - Fix missing SALU format bits - Remove unused isSALUInstr - Add isVALU - Switch isDS to use a bit like the others - Move SIInstrInfo::is* functions to header - Reorder so they are approximately sorted by type (SALU, VALU, memory) llvm-svn: 223038
* The andi16, addiusp and jraddiusp micromips instructions were missing ↵Vladimir Medic2014-12-012-0/+42
| | | | | | dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests. llvm-svn: 223006
* [PowerPC] Fix unwind info with dynamic stack realignmentJay Foad2014-12-011-12/+27
| | | | | | | | | | | | | | | | | | | | | | Summary: PowerPC DWARF unwind info defined CFA as SP + offset even in a function where the stack had been dynamically realigned. This clearly doesn't work because the offset from SP to CFA is not a constant. Fix it by defining CFA as BP instead. This was causing the AddressSanitizer null_deref test to fail 50% of the time, depending on whether SP happened to be 32-byte aligned on entry to a particular function or not. Reviewers: willschm, uweigand, hfinkel Reviewed By: hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6410 llvm-svn: 222996
* Add post-decode checking of HVC instruction.Charlie Turner2014-12-011-1/+23
| | | | | | | | | | | | Add checkDecodedInstruction for post-decode checking of instructions, to catch the corner cases like HVC that don't fit into the general pattern. Needed to check for an invalid condition field in instruction encoding despite HVC not taking a predicate. Patch by Matthew Wahab. Change-Id: I48e28de981d7a9e43569594da3c45fb478b4f795 llvm-svn: 222992
* Add Thumb HVC and ERET virtualisation extension instructions.Charlie Turner2014-12-012-0/+36
| | | | | | | Patch by Matthew Wahab. Change-Id: I131f71c1150d5fa797066a18e09d526c19bf9016 llvm-svn: 222990
* Add ARM ERET and HVC virtualisation extension instructions.Charlie Turner2014-12-013-3/+33
| | | | | | | Patch by Matthew Wahab. Change-Id: Iad75f078fbaa4ecc7d7a4820ad9b3930679cbbbb llvm-svn: 222989
* Fix capitalization. NFC.Akira Hatanaka2014-12-011-2/+2
| | | | llvm-svn: 222988
* [PowerPC] Add asm support for cache-inhibited ld/st instructionsHal Finkel2014-11-301-0/+18
| | | | | | | | | Add assembler support for the fixed-point cache-inhibited load/store instructions. These are hypervisor-level only, so don't get too excited ;) Fixes PR21650. llvm-svn: 222976
* Target triple OS detection tidyup. NFCSimon Pilgrim2014-11-292-5/+2
| | | | | | Use Triple::isOS*() helpers where possible. llvm-svn: 222960
* [mips][microMIPS] Implement NOP aliasesJozef Kolek2014-11-292-1/+4
| | | | | | | | | This patch implements microMIPS 16-bit (MOVE16 $0, $0) and 32-bit (SLL $0, $0, 0) NOP aliases. http://reviews.llvm.org/D6440 llvm-svn: 222953
* R600/SI: Fix assertion on sign extend of 3 vectorsMatt Arsenault2014-11-281-2/+2
| | | | | | | This was trying to create an MVT with 3x vectors which created an invalid EVT llvm-svn: 222942
* Revert "Masked Vector Load and Store Intrinsics."Duncan P. N. Exon Smith2014-11-284-166/+4
| | | | | | | | | | | This reverts commit r222632 (and follow-up r222636), which caused a host of LNT failures on an internal bot. I'll respond to the commit on the list with a reproduction of one of the failures. Conflicts: lib/Target/X86/X86TargetTransformInfo.cpp llvm-svn: 222936
* Enable FeatureFastUAMem for btver2Sanjay Patel2014-11-281-2/+8
| | | | | | | | | | | | | Allow unaligned 16-byte memop codegen for btver2. No functional changes for any other subtargets. Replace the existing supposed small memcpy test with an actual test of a small memcpy. The previous test wasn't using FileCheck either. This patch should allow us to close PR21541 ( http://llvm.org/bugs/show_bug.cgi?id=21541 ). Differential Revision: http://reviews.llvm.org/D6360 llvm-svn: 222925
* Fix wrong encoding of MRSBanked.Charlie Turner2014-11-281-1/+1
| | | | | | | Patch by Matthew Wahab. Change-Id: Ia2a001ca2760028ea360fe77b56f203a219eefbc llvm-svn: 222920
* Add missing 'override' keyword.Craig Topper2014-11-281-1/+1
| | | | llvm-svn: 222911
* Stop using ArrayRef of a const type.Tim Northover2014-11-272-2/+2
| | | | | | I *think* this is what the GCC bots are complaining about. llvm-svn: 222905
* AArch64: treat [N x Ty] as a block during procedure calls.Tim Northover2014-11-276-6/+155
| | | | | | | | | | | | | | The AAPCS treats small structs and homogeneous floating (or vector) aggregates specially, and guarantees they either get passed as a contiguous block of registers, or prevent any future use of those registers and get passed on the stack. This concept can fit quite neatly into LLVM's own type system, mapping an HFA to [N x float] and so on, and small structs to [N x i64]. Doing so allows front-ends to emit AAPCS compliant code without having to duplicate the register counting logic. llvm-svn: 222903
* [mips][microMIPS] Implement SWM16 and LWM16 instructionsZoran Jovanovic2014-11-277-0/+147
| | | | | | Differential Revision: http://reviews.llvm.org/D5579 llvm-svn: 222901
* [mips][microMIPS] Implement BREAK16 and SDBBP16 instructionsJozef Kolek2014-11-272-0/+17
| | | | | | | | Patch by Radovan Obradovic. Differential Revision: http://reviews.llvm.org/D5048 llvm-svn: 222900
* [mips] Add synci instruction.Daniel Sanders2014-11-273-1/+56
| | | | | | | | | | | | | | Patch by Amaury Pouly Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6421 llvm-svn: 222899
* [mips][microMIPS] Implement disassembler support for 16-bit instructions ↵Jozef Kolek2014-11-272-3/+69
| | | | | | | | LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 Differential Revision: http://reviews.llvm.org/D6419 llvm-svn: 222887
* Stop uppercasing build attribute data.Charlie Turner2014-11-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The string data for string-valued build attributes were being unconditionally uppercased. There is no mention in the ARM ABI addenda about case conventions, so it's technically implementation defined as to whether the data are capitialised in some way or not. However, there are good reasons not to captialise the data. * It's less work. * Some vendors may legitimately have case-sensitive checks for these attributes which would fail on LLVM generated object files. * There could be locale issues with uppercasing. The original reasons for uppercasing appear to have stemmed from an old codesourcery toolchain behaviour, see http://comments.gmane.org/gmane.comp.compilers.llvm.cvs/87133 This patch makes the object file emitted no longer captialise string data, it encodes as seen in the assembly source. Change-Id: Ibe20dd6e60d2773d57ff72a78470839033aa5538 llvm-svn: 222882
* R600/SI: Use ZeroOrNegativeOneBooleanContentMatt Arsenault2014-11-262-2/+3
| | | | | | | | | | | | | | This sort of doesn't matter since the setcc type is i1, but this previously was using the default UndefinedBooleanContent. This makes it more consistent with R600. This enables more optimizations which typically give up on UndefinedBooleanContent. For example, there is already a special case target DAG combine for setcc + sext which can be eliminated in favor of what the generic DAG combiner can do if it assumes boolean values are sign extended. Since -1 is an inline immediate, using it is basically free and the backend already uses it when a boolean value is needed in a wider type. llvm-svn: 222850
* [Hexagon] Adding cmp* immediate form instructions.Colin LeMahieu2014-11-264-62/+68
| | | | llvm-svn: 222849
* [mips][microMIPS] Implement disassembler support for 16-bit instructions ↵Jozef Kolek2014-11-263-4/+67
| | | | | | | | LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
* [Hexagon] Adding and64, or64, and xor64 instructions.Colin LeMahieu2014-11-261-0/+13
| | | | llvm-svn: 222846
* R600/SI: Create e64 versions of and/or/xor in SILowerI1CopiesMatt Arsenault2014-11-261-3/+3
| | | | | | | | | This fixes moving boolean constants into registers before operating on them. They get permuted and shrunk down to e32 anyway later. This is a temporary fix until the patch that removes these pseudos is committed. llvm-svn: 222844
* Update AArch64 ELF relocations to ABI 1.0Will Newton2014-11-261-1/+1
| | | | | | | | | | | | | | | | | | | | This mostly entails adding relocations, however there are a couple of changes to existing relocations: 1. R_AARCH64_NONE is defined to be zero rather than 256 R_AARCH64_NONE has been defined to be zero for a long time elsewhere e.g. binutils and glibc since the submission of the AArch64 port in 2012 so this is required for compatibility. 2. R_AARCH64_TLSDESC_ADR_PAGE renamed to R_AARCH64_TLSDESC_ADR_PAGE21 I don't think there is any way for relocation names to leak out of LLVM so this should not break anything. Tested with check-all with no regressions. llvm-svn: 222821
* AVX-512: Scalar ERI intrinsicsElena Demikhovsky2014-11-264-60/+103
| | | | | | | | | | | | including SAE mode and memory operand. Added AVX512_maskable_scalar template, that should cover all scalar instructions in the future. The main difference between AVX512_maskable_scalar<> and AVX512_maskable<> is using X86select instead of vselect. I need it, because I can't create vselect node for MVT::i1 mask for scalar instruction. http://reviews.llvm.org/D6378 llvm-svn: 222820
* Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.Craig Topper2014-11-2634-298/+298
| | | | llvm-svn: 222801
* [X86][SSE] Improvements to byte shift shuffle matchingSimon Pilgrim2014-11-251-20/+20
| | | | | | | | Since (v)pslldq / (v)psrldq instructions resolve to a single input argument it is useful to match it much earlier than we currently do - this prevents more complicated shuffles (notably insertion into a zero vector) matching before it. Differential Revision: http://reviews.llvm.org/D6409 llvm-svn: 222796
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