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* This patch implements parsing of mips FCC register operands. The example ↵Vladimir Medic2013-07-304-14/+66
| | | | | | instructions have been added to test files. llvm-svn: 187410
* [ARM] check bitwidth in PerformORCombineSaleem Abdulrasool2013-07-301-14/+21
| | | | | | | | | | | | | When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the bitwidth of the second operands to both ands match before comparing the negation of the values. Split the check of the value of the second operands to the ands. Move the cast and variable declaration slightly higher to make it slightly easier to follow. Bug-Id: 16700 Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org> llvm-svn: 187404
* [Sparc] Use call's debugloc for the unimp instruction.Venkatraman Govindaraju2013-07-301-1/+1
| | | | llvm-svn: 187402
* [PowerPC] Skeletal FastISel support for 64-bit PowerPC ELF.Bill Schmidt2013-07-305-1/+347
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the first of many upcoming patches for PowerPC fast instruction selection support. This patch implements the minimum necessary for a functional (but extremely limited) FastISel pass. It allows the table-generated portions of the selector to be created and used, but in most cases selection will fall back to the DAG selector. None of the block terminator instructions are implemented yet, and most interesting instructions require some special handling. Therefore there aren't any new test cases with this patch. There will be quite a few tests coming with future patches. This patch adds the make/CMake support for the new code (including tablegen -gen-fast-isel) and creates the FastISel object for PPC64 ELF only. It instantiates the necessary virtual functions (TargetSelectInstruction, TargetMaterializeConstant, TargetMaterializeAlloca, tryToFoldLoadIntoMI, and FastLowerArguments), but of these, only TargetMaterializeConstant contains any useful implementation. This is present since the table-generated code requires the ability to materialize integer constants for some instructions. This patch has been tested by building and running the projects/test-suite code with -O0. All tests passed with the exception of a couple of long-running tests that time out using -O0 code generation. llvm-svn: 187399
* [R600] Replicate old DAGCombiner behavior in target specific DAG combine.Quentin Colombet2013-07-301-0/+56
| | | | | | | build_vector is lowered to REG_SEQUENCE, which is something the register allocator does a good job at optimizing. llvm-svn: 187397
* [mips] Add comment and simplify function.Akira Hatanaka2013-07-291-23/+14
| | | | llvm-svn: 187371
* Use proper section suffix for COFF weak symbolsNico Rieck2013-07-291-12/+17
| | | | | | | | | 32-bit symbols have "_" as global prefix, but when forming the name of COMDAT sections this prefix is ignored. The current behavior assumes that this prefix is always present which is not the case for 64-bit and names are truncated. llvm-svn: 187356
* Proper va_arg/va_copy lowering on win64Nico Rieck2013-07-291-1/+3
| | | | | | | Win64 uses CharPtrBuiltinVaList instead of X86_64ABIBuiltinVaList like other 64-bit targets. llvm-svn: 187355
* Allow generation of vmla.f32 instructions when targeting Cortex-A15. The ↵Silviu Baranga2013-07-294-4/+6
| | | | | | patch also adds the VFP4 feature to Cortex-A15 and fixes the DontUseFusedMAC predicate so that we can still generate vmla.f32 instructions on non-darwin targets with VFP4. llvm-svn: 187349
* test commitRobert Lytton2013-07-291-0/+1
| | | | llvm-svn: 187348
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-2813-22/+441
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. llvm-svn: 187324
* [PowerPC] Add comment explaining preprocessor directive.Bill Schmidt2013-07-281-0/+2
| | | | llvm-svn: 187320
* Revert 187318Bill Schmidt2013-07-281-1/+1
| | | | llvm-svn: 187319
* [PowerPC] Remove unnecessary preprocessor checking.Bill Schmidt2013-07-281-1/+1
| | | | | | | | | The tests !defined(__ppc__) && !defined(__powerpc__) are not needed or helpful when verifying that code is being compiled for a 64-bit target. The simpler test provided by this revision is sufficient to tell if the target is 64-bit. llvm-svn: 187318
* Create a constant pool symbol for the GOT in the ARMCGBR the same way weChandler Carruth2013-07-271-7/+8
| | | | | | | | | | | | | | do in the SDag when lowering references to the GOT: use ARMConstantPoolSymbol rather than creating a dummy global variable. The computation of the alignment still feels weird (it uses IR types and datalayout) but it preserves the exact previous behavior. This change fixes the memory leak of the global variable detected on the valgrind leak checking bot. Thanks to Benjamin Kramer for pointing me at ARMConstantPoolSymbol to handle this use case. llvm-svn: 187303
* Fix yet another memory leak found by the vg-leak bot. Folks (includingChandler Carruth2013-07-271-2/+6
| | | | | | | | | | | | | | | | me) should start watching this bot more as its catching lots of bugs. The fix here is to not construct the global if we aren't going to need it. That's cheaper anyways, and globals have highly predictable types in practice. I've added an assert to catch skew between our manual testing of the type and the actual type just for paranoia's sake. Note that this pattern is actually fine in most globals because when you build a global with a module it automatically is moved to be owned by that module. But here, we're in isel and don't really want to do that. The solution of not creating a global is simpler anyways. llvm-svn: 187302
* Fix a memory leak in the hexagon scheduler. We call initialize here moreChandler Carruth2013-07-271-0/+2
| | | | | | | | | | | | | than once, and the second time through we leaked memory. Found thanks to the vg-leak bot, but I can't locally reproduce it with valgrind. The debugger confirms that it is in fact leaking here. This whole code is totally gross. Why is initialize being called on each runOnFunction??? Why aren't these OwningPtr<>s, and why aren't their lifetimes better defined? Anyways, this is just a surgical change to help out the leak checking bots. llvm-svn: 187299
* SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch ↵Tom Stellard2013-07-275-0/+110
| | | | | | | | | | | | | | conditions Merge consecutive if-regions if they contain identical statements. Both transformations reduce number of branches. The transformation is guarded by a target-hook, and is currently enabled only for +R600, but the correctness has been tested on X86 target using a variety of CPU benchmarks. Patch by: Mei Ye llvm-svn: 187278
* Revert "[PowerPC] Improve consistency in use of __ppc__, __powerpc__, etc."Rafael Espindola2013-07-261-3/+3
| | | | | | This reverts commit r187248. It broke many bots. llvm-svn: 187254
* [PowerPC] Improve consistency in use of __ppc__, __powerpc__, etc.Bill Schmidt2013-07-261-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Both GCC and LLVM will implicitly define __ppc__ and __powerpc__ for all PowerPC targets, whether 32- or 64-bit. They will both implicitly define __ppc64__ and __powerpc64__ for 64-bit PowerPC targets, and not for 32-bit targets. We cannot be sure that all other possible compilers used to compile Clang/LLVM define both __ppc__ and __powerpc__, for example, so it is best to check for both when relying on either inside the Clang/LLVM code base. This patch makes sure we always check for both variants. In addition, it fixes one unnecessary check in lib/Target/PowerPC/PPCJITInfo.cpp. (At least one of __ppc__ and __powerpc__ should always be defined when compiling for a PowerPC target, no matter which compiler is used, so testing for them is unnecessary.) There are some places in the compiler that check for other variants, like __POWERPC__ and _POWER, and I have left those in place. There is no need to add them elsewhere. This seems to be in Apple-specific code, and I won't take a chance on breaking it. There is no intended change in behavior; thus, no test cases are added. llvm-svn: 187248
* [mips] Implement llvm.trap intrinsic.Akira Hatanaka2013-07-262-0/+7
| | | | | | Patch by Sasa Stankovic. llvm-svn: 187244
* [mips] Fix FP conditional move instructions to have explicit FP condition codeAkira Hatanaka2013-07-264-13/+14
| | | | | | register operands. llvm-svn: 187242
* [mips] Fix FP branch instructions to have explicit FP condition code registerAkira Hatanaka2013-07-265-25/+41
| | | | | | operands. llvm-svn: 187238
* [mips] Increase the number of floating point condition code registers to eight.Akira Hatanaka2013-07-261-3/+5
| | | | llvm-svn: 187234
* [mips] Fix floating point branch, comparison, and conditional move instructionsAkira Hatanaka2013-07-262-4/+4
| | | | | | | | | to have register FCC0 (the first floating point condition code register) in their Uses/Defs list. No intended functionality change. llvm-svn: 187233
* [mips] Delete register print method MipsInstPrinter::printCPURegs that is notAkira Hatanaka2013-07-263-11/+5
| | | | | | | | needed. The generic method printOperand will do. No functionality change. llvm-svn: 187231
* [mips] Print instructions "beq", "bne" and "or" using assembler pseudoAkira Hatanaka2013-07-262-1/+57
| | | | | | | | | | instructions "beqz", "bnez" and "move", when possible. beq $2, $zero, $L1 => beqz $2, $L1 bne $2, $zero, $L1 => bnez $2, $L1 or $2, $3, $zero => move $2, $3 llvm-svn: 187229
* Add a target legalize hook for SplitVectorOperand (again)Justin Holewinski2013-07-261-1/+1
| | | | | | | | | | | | | | CustomLowerNode was not being called during SplitVectorOperand, meaning custom legalization could not be used by targets. This also adds a test case for NVPTX that depends on this custom legalization. Differential Revision: http://llvm-reviews.chandlerc.com/D1195 Attempt to fix the buildbots by making the X86 test I just added platform independent llvm-svn: 187202
* Revert "Add a target legalize hook for SplitVectorOperand"Rafael Espindola2013-07-261-1/+1
| | | | | | | | | | This reverts commit 187198. It broke the bots. The soft float test probably needs a -triple because of name differences. On the hard float test I am getting a "roundss $1, %xmm0, %xmm0", instead of "vroundss $1, %xmm0, %xmm0, %xmm0". llvm-svn: 187201
* Add a target legalize hook for SplitVectorOperandJustin Holewinski2013-07-261-1/+1
| | | | | | | | | | | | CustomLowerNode was not being called during SplitVectorOperand, meaning custom legalization could not be used by targets. This also adds a test case for NVPTX that depends on this custom legalization. Differential Revision: http://llvm-reviews.chandlerc.com/D1195 llvm-svn: 187198
* test commitRichard Osborne2013-07-261-1/+1
| | | | llvm-svn: 187195
* [XCore] Add TODO regarding byval structsRichard Osborne2013-07-261-0/+2
| | | | llvm-svn: 187193
* Fix more Intel syntax issues with FP instruction aliases. Test cases coming ↵Craig Topper2013-07-261-8/+8
| | | | | | in a subsequent patch. llvm-svn: 187187
* Take advantage of the register enums being in order to remove a couple ↵Craig Topper2013-07-261-18/+4
| | | | | | static tables. llvm-svn: 187182
* [PowerPC] Support powerpc64le as a syntax-checking target.Bill Schmidt2013-07-2610-7/+44
| | | | | | | | | | | | | | | | | | | | | | | This patch provides basic support for powerpc64le as an LLVM target. However, use of this target will not actually generate little-endian code. Instead, use of the target will cause the correct little-endian built-in defines to be generated, so that code that tests for __LITTLE_ENDIAN__, for example, will be correctly parsed for syntax-only testing. Code generation will otherwise be the same as powerpc64 (big-endian), for now. The patch leaves open the possibility of creating a little-endian PowerPC64 back end, but there is no immediate intent to create such a thing. The LLVM portions of this patch simply add ppc64le coverage everywhere that ppc64 coverage currently exists. There is nothing of any import worth testing until such time as little-endian code generation is implemented. In the corresponding Clang patch, there is a new test case variant to ensure that correct built-in defines for little-endian code are generated. llvm-svn: 187179
* PPC32 va_list is an actual structure so va_copy needs to copy the wholeRoman Divacky2013-07-252-1/+23
| | | | | | | structure not just a pointer. This implements that and thus fixes va_copy on PPC32. Fixes #15286. Both bug and patch by Florian Zeitz! llvm-svn: 187158
* Remove the mblaze backend from llvm.Rafael Espindola2013-07-2572-10025/+1
| | | | | | Approval in here http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-July/064169.html llvm-svn: 187145
* AArch64: fix even more JIT failuresTim Northover2013-07-252-4/+4
| | | | | | | The last patch corrected some issues, but constant-pool entries had actual codegen bugs in the large memory model (which MCJIT uses). llvm-svn: 187126
* [SystemZ] Rework compare and branch supportRichard Sandiford2013-07-255-62/+129
| | | | | | | | | | | | | | Before the patch we took advantage of the fact that the compare and branch are glued together in the selection DAG and fused them together (where possible) while emitting them. This seemed to work well in practice. However, fusing the compare so early makes it harder to remove redundant compares in cases where CC already has a suitable value. This patch therefore uses the peephole analyzeCompare/optimizeCompareInstr pair of functions instead. No behavioral change intended, but it paves the way for a later patch. llvm-svn: 187116
* [SystemZ] Add LOCR and LOCGRRichard Sandiford2013-07-255-0/+118
| | | | llvm-svn: 187113
* [SystemZ] Add LOC and LOCGRichard Sandiford2013-07-254-0/+75
| | | | | | | As with the stores, these instructions can trap when the condition is false, so they are only used for things like (cond ? x : *ptr). llvm-svn: 187112
* [SystemZ] Add STOC and STOCGRichard Sandiford2013-07-257-51/+126
| | | | | | | | These instructions are allowed to trap even if the condition is false, so for now they are only used for "*ptr = (cond ? x : *ptr)"-style constructs. llvm-svn: 187111
* Replace the "NoFramePointerElimNonLeaf" target option with a function attribute.Bill Wendling2013-07-251-1/+0
| | | | | | | | There's no need to specify a flag to omit frame pointer elimination on non-leaf nodes...(Honestly, I can't parse that option out.) Use the function attribute stuff instead. llvm-svn: 187093
* [mips] Make MipsAsmParser::parseCCRRegs return NoMatch instead of ParseFailAkira Hatanaka2013-07-241-2/+2
| | | | | | | when there wasn't a match. This behavior is consistent with other register parsing methods. llvm-svn: 187063
* [test commit] Minor comment change.Petar Jovanovic2013-07-241-3/+3
| | | | | | Testing commit access credentials. llvm-svn: 187032
* I'm starting to commit KNL backend. I'll push patches one-by-one. This patch ↵Elena Demikhovsky2013-07-248-27/+190
| | | | | | | | includes support for the extended register set XMM16-31, YMM16-31, ZMM0-31. The full ISA you can see here: http://software.intel.com/en-us/intel-isa-extensions llvm-svn: 187030
* allow tests to run on powerpc-darwin8 again, checking for __ppc__David Fang2013-07-241-2/+2
| | | | llvm-svn: 187027
* Split generated asm mnemonic matching table into a separate table for each ↵Craig Topper2013-07-245-1/+5
| | | | | | | | asm variant. This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o. llvm-svn: 187026
* Revert accidental commit.Craig Topper2013-07-241-1/+1
| | | | llvm-svn: 187021
* Fix aliases for shrd/shld to handle Intel syntax properly. Also suppress ↵Craig Topper2013-07-242-14/+14
| | | | | | them from being used by the asm printer. llvm-svn: 187020
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