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* [X86] Check that attribute parameters match for tail calls (PR26590)Hans Wennborg2016-03-011-3/+24
| | | | | | | | | | | | In the code below on 32-bit targets, x would previously get forwarded to g() without sign-extension to 32 bits as required by the parameter attribute. void g(signed short); void f(unsigned short x) { g(x); } llvm-svn: 262352
* fix documentation comments; NFCSanjay Patel2016-03-011-85/+74
| | | | llvm-svn: 262351
* function names start with a lowercase letter; NFCSanjay Patel2016-03-011-12/+12
| | | | llvm-svn: 262347
* [AMDGPU] Remove unused disassembler code.Nikolay Haustov2016-03-011-2/+0
| | | | llvm-svn: 262346
* [AMDGPU] Fix build warnings.Nikolay Haustov2016-03-011-2/+2
| | | | llvm-svn: 262338
* [AMDGPU] Disassembler code refactored + error messages.Nikolay Haustov2016-03-013-385/+308
| | | | | | | | | | | | | | | | | | Idea behind this change is to make code shorter and as much common for all targets as possible. Let's even accept more code than is valid for a particular target, leaving it for the assembler to sort out. 64bit instructions decoding added. Error\warning messages on unrecognized instructions operands added, InstPrinter allowed to print invalid operands helping to find invalid/unsupported code. The change is massive and hard to compare with previous version, so it makes sense just to take a look on the new version. As a bonus, with a few TD changes following, it disassembles the majority of instructions. Currently it fully disassembles >300K binary source of some blas kernel. Previous TODOs were saved whenever possible. Patch by: Valery Pykhtin Differential Revision: http://reviews.llvm.org/D17720 llvm-svn: 262332
* [AVX512][PSRAQ][PSRAD] Change imm8 to int.Michael Zuckerman2016-03-011-6/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D17692 llvm-svn: 262320
* Disallow generating vzeroupper before return instruction (iret) in interrupt ↵Amjad Aboud2016-03-011-3/+8
| | | | | | | | | | handler function. This resolves https://llvm.org/bugs/show_bug.cgi?id=26412 Differential Revision: http://reviews.llvm.org/D17542 llvm-svn: 262319
* [mips] Promote the result of SETCC nodes to GPR width.Vasileios Kalintiris2016-03-0114-418/+550
| | | | | | | | | | | | | | | | | | | | Summary: This patch modifies the existing comparison, branch, conditional-move and select patterns, and adds new ones where needed. Also, the updated SLT{u,i,iu} set of instructions generate a GPR width result. The majority of the code changes in the Mips back-end fix the wrong assumption that the result of SETCC nodes always produce an i32 value. The changes in the common code path account for the fact that in 64-bit MIPS targets, i1 is promoted to i32 instead of i64. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D10970 llvm-svn: 262316
* [TableGen] AsmMatcher: Skip optional operands in the midle of instruction if ↵Nikolay Haustov2016-03-012-24/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | it is not present Previosy, if actual instruction have one of optional operands then other optional operands listed before this also should be presented. For example instruction v_fract_f32 v0, v1, mul:2 have one optional operand - OMod and do not have optional operand clamp. Previously this was not allowed because clamp is listed before omod in AsmString: string AsmString = "v_fract_f32$vdst, $src0_modifiers$clamp$omod"; Making this work required some hacks (both OMod and Clamp match classes have same PredicateMethod). Now, if MatchInstructionImpl meets formal optional operand that is not presented in actual instruction it skips this formal operand and tries to match current actual operand with next formal. Patch by: Sam Kolton Review: http://reviews.llvm.org/D17568 [AMDGPU] Assembler: Check immediate types for several optional operands in predicate methods With this change you should place optional operands in order specified by asm string: clamp -> omod offset -> glc -> slc -> tfe Fixes for several tests. Depends on D17568 Patch by: Sam Kolton Review: http://reviews.llvm.org/D17644 llvm-svn: 262314
* [X86] Centralize the masking of TSFlags with FormMask into a variable ↵Craig Topper2016-03-011-6/+3
| | | | | | earlier so we can stop masking in multiple places. NFC llvm-svn: 262312
* [X86] Localize a temporary variable into the cases its need in. NFCCraig Topper2016-03-011-10/+9
| | | | llvm-svn: 262310
* [X86] Be consistent about using pre/post increment/decrement in nearby code. NFCCraig Topper2016-03-011-4/+4
| | | | llvm-svn: 262309
* [X86] Combine some initialization code with variable declaration and ↵Craig Topper2016-03-011-41/+28
| | | | | | comments. NFC llvm-svn: 262301
* AMDGPU: Don't emit build_pair during udivrem legalizationMatt Arsenault2016-03-011-6/+11
| | | | | | | | Technically you aren't supposed to emit these after type legalization for some reason, and we use vector extracts of bitcasted integers as the canonical way to do this. llvm-svn: 262298
* AMDGPU: Don't use estimated stack size when we know the real stack sizeMatt Arsenault2016-03-011-1/+1
| | | | llvm-svn: 262297
* AMDGPU: Set HasExtractBitInsnMatt Arsenault2016-03-011-0/+11
| | | | | | | | | | This currently does not have the control over the bitwidth, and there are missing optimizations to reduce the integer to 32-bit if it can be. But in most situations we do want the sinking to occur. llvm-svn: 262296
* Simplify some boolean conditional return statements in AArch64.Eric Christopher2016-02-297-48/+18
| | | | | | | | http://reviews.llvm.org/D9979 Patch by Richard Thomson (and some conflict resolution by me). llvm-svn: 262266
* [Hexagon] As a size optimization, not lazy extending TPREL or DTPREL ↵Colin LeMahieu2016-02-291-8/+14
| | | | | | variants since they're usually in range. llvm-svn: 262258
* [Hexagon] Missed member initialization causing ubsan failure.Colin LeMahieu2016-02-291-1/+2
| | | | llvm-svn: 262252
* [AArch64] Fix isLegalAddImmediate() to return true for valid negative values.Geoff Berry2016-02-291-2/+2
| | | | | | | | | | Reviewers: t.p.northover, jmolloy Subscribers: mcrosier, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D17463 llvm-svn: 262248
* [X86] Move the ATOMIC_LOAD_OP ISel from DAGToDAG to ISelLowering. NFCI.Ahmed Bougacha2016-02-295-340/+166
| | | | | | | | | | | | | | This is long-standing dirtiness, as acknowledged by r77582: The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. Doing this before selection will let us combine away some constructs. Differential Revision: http://reviews.llvm.org/D17659 llvm-svn: 262244
* [Hexagon] Setting sign mismatch flag on expression instead of using bit tricks.Colin LeMahieu2016-02-293-16/+22
| | | | llvm-svn: 262243
* [WinEH] Make setjmp work correctly with EHDavid Majnemer2016-02-291-20/+136
| | | | | | | | | | | | | | | | | | | | 32-bit X86 EH on Windows utilizes a stack of registration nodes allocated and deallocated on entry/exit. A registration node contains a bunch of EH personality specific information like which try-state we are currently in. Because a setjmp target allows control flow from arbitrary program points, there is no way to ensure that the try-state we are in is correctly updated once we transfer control. MSVC compatible compilers, like MSVC and ICC, utilize runtime helpers to reinitialize the try-state when a longjmp occurs. This is implemented by adding additional arguments to _setjmp3: the desired try-state and a helper routine to update the try-state. Differential Revision: http://reviews.llvm.org/D17721 llvm-svn: 262241
* [Hexagon] Using MustExtend flag on expression instead of passing around bools.Colin LeMahieu2016-02-294-55/+64
| | | | llvm-svn: 262238
* Fix for PR26180Nemanja Ivanovic2016-02-293-6/+6
| | | | | | | | | | Corresponds to Phabricator review: http://reviews.llvm.org/D16592 This fix includes both an update to how we handle the "generic" CPU on LE systems as well as Anton's fix for the Fast Isel issue. llvm-svn: 262233
* [mips] Range check uimm20 and fixed a bug this revealed.Daniel Sanders2016-02-298-76/+57
| | | | | | | | | | | | | | | | | | | Summary: The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when printing assembly. This came up when replacing MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary bit widths. MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been removed. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15521 llvm-svn: 262231
* [mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined.Vasileios Kalintiris2016-02-291-1/+2
| | | | | | | | | | Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15420 llvm-svn: 262230
* [mips] Make isel select the correct DEXT variant up front.Daniel Sanders2016-02-295-34/+44
| | | | | | | | | | | | | | | | | Summary: Previously, it would always select DEXT and substitute any invalid matches for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works but causes problems when adding range checked immediates to IAS. Now isel selects the correct variant up front. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16810 llvm-svn: 262229
* [mips] Make symbols an acceptable branch target when expanding ↵Daniel Sanders2016-02-291-1/+2
| | | | | | | | | | | | compare-to-immediate-and-branch macros. Reviewers: vkalintiris Subscribers: llvm-commits, vkalintiris, dim, seanbruno, dsanders Differential Revision: http://reviews.llvm.org/D15369 llvm-svn: 262213
* [mips] Remove unused function declarations from MipsRegisterInfo.h. NFC.Vasileios Kalintiris2016-02-281-10/+0
| | | | llvm-svn: 262187
* WebAssembly: fix buildJF Bastien2016-02-282-3/+3
| | | | | | More API churn, experimental target got sad. llvm-svn: 262179
* [AVX512][PSLLW ][PSLLV] Change imm8 to intMichael Zuckerman2016-02-281-3/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D17684 llvm-svn: 262176
* AMDGPU: More bits of frame index are known to be zeroMatt Arsenault2016-02-274-29/+26
| | | | | | | | | | | | The maximum private allocation for the whole GPU is 4G, so the maximum possible index for a single workitem is the maximum size divided by the smallest granularity for a dispatch. This increases the number of known zero high bits, which enables more offset folding. The maximum private size per workitem with this is 128M but may be smaller still. llvm-svn: 262153
* CodeGen: Update LiveIntervalAnalysis API to use MachineInstr&, NFCDuncan P. N. Exon Smith2016-02-271-2/+2
| | | | | | These parameters aren't expected to be null, so take them by reference. llvm-svn: 262151
* CodeGen: Change MachineInstr to use MachineInstr&, NFCDuncan P. N. Exon Smith2016-02-277-12/+12
| | | | | | | | Change MachineInstr API to prefer MachineInstr& over MachineInstr* whenever the parameter is expected to be non-null. Slowly inching toward being able to fix PR26753. llvm-svn: 262149
* AArch64: Use MachineInstr& in guaranteesZeroRegInBlock(), NFCDuncan P. N. Exon Smith2016-02-271-6/+6
| | | | llvm-svn: 262143
* CodeGen: Update DFAPacketizer API to take MachineInstr&, NFCDuncan P. N. Exon Smith2016-02-274-75/+78
| | | | | | | | | In all but one case, change the DFAPacketizer API to take MachineInstr& instead of MachineInstr*. In DFAPacketizer::endPacket(), take MachineBasicBlock::iterator. Besides cleaning up the API, this is in search of PR26753. llvm-svn: 262142
* WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFCDuncan P. N. Exon Smith2016-02-276-10/+10
| | | | | | | | Update APIs in MachineInstrBundle.h to take and return MachineInstr& instead of MachineInstr* when the instruction cannot be null. Besides being a nice cleanup, this is tacking toward a fix for PR26753. llvm-svn: 262141
* WebAssembly: fix buildJF Bastien2016-02-271-8/+8
| | | | | | It was broken by the work for PR26753. llvm-svn: 262140
* Tidyup for loops - don't repeat upper limit evaluation if you don't have to. ↵Simon Pilgrim2016-02-271-5/+5
| | | | | | NFCI. llvm-svn: 262137
* The patch adds missing registers and instructions to complete all the ↵Chris Dewhurst2016-02-274-18/+310
| | | | | | | | | | | | | registers supported by the Sparc v8 manual. These are all co-processor registers, with the exception of the floating-point deferred-trap queue register. Although these will not be lowered automatically by any instructions, it allows the use of co-processor instructions implemented by inline-assembly. Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td, which was formerly causing a problem in the disassembly of the %fq register. llvm-svn: 262133
* Strip trailing whitespace. NFCI.Simon Pilgrim2016-02-271-9/+9
| | | | llvm-svn: 262131
* AMDGPU: Split vi-insts subtarget featureMatt Arsenault2016-02-273-6/+24
| | | | | | | This will be more useful for marking builtins acceptable for which subtargets. llvm-svn: 262121
* AMDGPU: Add s_sleep intrinsicMatt Arsenault2016-02-272-1/+17
| | | | llvm-svn: 262120
* AMDGPU: Implement readcyclecounterMatt Arsenault2016-02-277-10/+68
| | | | | | | | | | This matches the behavior of the HSAIL clock instruction. s_realmemtime is used if the subtarget supports it, and falls back to s_memtime if not. Also introduces new intrinsics for each of s_memtime / s_memrealtime. llvm-svn: 262119
* CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFCDuncan P. N. Exon Smith2016-02-275-21/+21
| | | | | | | | | | | | | | Take MachineInstr by reference instead of by pointer in SlotIndexes and the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are never null, so this cleans up the API a bit. It also incidentally removes a few implicit conversions from MachineInstrBundleIterator to MachineInstr* (see PR26753). At a couple of call sites it was convenient to convert to a range-based for loop over MachineBasicBlock::instr_begin/instr_end, so I added MachineBasicBlock::instrs. llvm-svn: 262115
* [X86] Fix a stale comment. NFC.Ahmed Bougacha2016-02-261-2/+2
| | | | llvm-svn: 262087
* [X86] Remove the unused SDTX86atomicBinary. NFC.Ahmed Bougacha2016-02-261-2/+0
| | | | llvm-svn: 262086
* Strip trailing whitespace. NFCI.Simon Pilgrim2016-02-262-10/+10
| | | | llvm-svn: 262083
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