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* [X86] Remove unnecessary if statement from LowerBUILD_VECTOR. NFCICraig Topper2018-01-151-1/+1
| | | | | | We were checking for 128, 256, or 512 bit vectors, but those are the only types that can get here. llvm-svn: 322510
* [WebAssembly] Update README.txt.Dan Gohman2018-01-151-13/+41
| | | | | | | Describe more of the current status, mention Rust as another easy way to use this backend, and add more documentation links. llvm-svn: 322508
* [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32Stanislav Mekhanoshin2018-01-154-4/+19
| | | | | | Differential Revision: https://reviews.llvm.org/D41617 llvm-svn: 322500
* [Hexagon] Implement signed and unsigned multiply-high for vectorsKrzysztof Parzyszek2018-01-154-3/+166
| | | | llvm-svn: 322499
* [Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectorsKrzysztof Parzyszek2018-01-151-38/+115
| | | | | | | The old implementation was not always correct. The new one recognizes more shuffles that match specific instructions. llvm-svn: 322498
* [AMDGPU] Copy impdefs from pseudo to real instructionsStanislav Mekhanoshin2018-01-154-0/+4
| | | | | | | | | | In some cases we do not copy implicit defs from pseudo to real VOP instructions. It has no visible impact at the moment thus no tests are affected or added. Differential Revision: https://reviews.llvm.org/D41783 llvm-svn: 322496
* [X86] Fix typos in WriteVMOVNTDQSt and WriteVMOVNTPYSt pattern names. NFCI.Simon Pilgrim2018-01-151-5/+5
| | | | llvm-svn: 322495
* [SystemZ] Check for legality before doing LOAD AND TEST transformations.Jonas Paulsson2018-01-151-52/+79
| | | | | | | | | | Since a load and test instruction treat its operands as signed, it can only replace a logical compare for EQ/NE uses. Review: Ulrich Weigand https://bugs.llvm.org/show_bug.cgi?id=35662 llvm-svn: 322488
* [X86] Add missing predicates for VRNDSCALES{D,S}{m,r}Clement Courbet2018-01-151-1/+1
| | | | | | | | | | | | Summary: This is similar to https://reviews.llvm.org/D41983. Reviewers: gchatelet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42069 llvm-svn: 322486
* Update BTVER2 sched numbers for some AVX instructions (xmm version).Andrew V. Tischenko2018-01-151-3/+42
| | | | | | Differential Revision: https://reviews.llvm.org/D40067 llvm-svn: 322485
* [X86]Add missing predicates for VMOVDQUYrm,VMOVDQUYmr.Clement Courbet2018-01-151-6/+3
| | | | | | | | | | | | | | | Summary: Due to missing parentheses. This is similar to https://reviews.llvm.org/D41983. Reviewers: gchatelet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42062 llvm-svn: 322483
* [AArch64][AsmParser] Cleanup isSImm7s4, isSImm7s8, (etc) functions.Sander de Smalen2018-01-152-44/+22
| | | | | | | | | | | | Reviewers: fhahn, rengolin, t.p.northover, echristo, olista01, samparker Reviewed By: fhahn, samparker Subscribers: samparker, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41899 llvm-svn: 322481
* [X86] Fix missing predicates HasAVX512 Predicates in avx512_sqrt_scalar.Clement Courbet2018-01-151-38/+39
| | | | | | | | | | | | | | Summary: For example, VSQRTSDZr and VSQRTSSZr were missing the predicate. Also fix braces indentation and braces for consistency. Reviewers: craig.topper, RKSimon Suscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41983 llvm-svn: 322478
* [X86][SSE] Support combining MOVLHPS undef inputsSimon Pilgrim2018-01-141-0/+1
| | | | llvm-svn: 322459
* [X86] Use ISD::TRUNCATE instead of X86ISD::VTRUNC when input and output ↵Craig Topper2018-01-143-70/+72
| | | | | | types have the same number of elements. llvm-svn: 322455
* [X86] Add X86ISD::VTRUNC to computeKnownBitsForTargetNode.Craig Topper2018-01-141-0/+12
| | | | | | | | We have to take special care to avoid the cases where the result of the truncate would be padded with zero elements. Ideally we'd just use ISD::TRUNCATE for these cases instead. llvm-svn: 322454
* [X86] Improve legalization of vXi16/vXi8 selects.Craig Topper2018-01-142-5/+14
| | | | | | | | Extend vXi1 conditions of vXi8/vXi16 selects even before type legalization gets a chance to split wide vectors. Previously we would only extend 128 and 256 bit vectors. But if we start with a 512 bit vector or wider that needs to be split we wouldn't extend until after the split had taken place. By extending early we improve the results of type legalization. Don't widen condition of 128/256 bit vXi16/vXi8 selects when we have BWI but not VLX. We can still use a mask register by widening the select to 512-bits instead. This is similar to what we do for compares already. llvm-svn: 322450
* X86: Add pattern matching for PMADDWDZvi Rackover2018-01-131-0/+110
| | | | | | | | | | | | | | | In addition to the existing match as part of a loop-reduction, add a straightforward pattern match for DAG-contained patterns. Reviewers: RKSimon, craig.topper Subscribers: llvm-commits Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D41811 llvm-svn: 322446
* [X86] Add DAG combine to promote vXi1 result of a vXi8/vXi16 setcc when we ↵Craig Topper2018-01-131-1/+15
| | | | | | | | have AVX512 but not BWI. This avoids having the result type stick around until lowering where we have to extend the setcc and insert a truncate. If we get the types converted early we can do more to optimize it. llvm-svn: 322432
* [MachineOutliner] Move hasAddressTaken check to MachineOutliner.cppJessica Paquette2018-01-131-4/+0
| | | | | | | | | | | | | *Mostly* NFC. Still updating the test though just for completeness. This moves the hasAddressTaken check to MachineOutliner.cpp and replaces it with a per-basic block test rather than a per-function test. The old test was too conservative and was preventing functions in C programs from being outlined even though they were safe to outline. This was mostly a problem in C sources. llvm-svn: 322425
* [AMDGPU] stop image_store being moved illegallyTim Renouf2018-01-121-6/+2
| | | | | | | | | | | | | | | | | | | | Summary: A recent change 321556: AMDGPU: Remove mayLoad/hasSideEffects from MIMG stores can allow the machine instruction scheduler to move an image store past an image load using the same descriptor. V2: Fixed by marking image ops as mayAlias and isAliased. This may be overly conservative, and we may need to revisit. V3: Reverted test change done on 321556. Reviewers: arsenm, nhaehnle, dstuttard Subscribers: llvm-commits, t-tye, yaxunl, wdng, kzhuravl Differential Revision: https://reviews.llvm.org/D41969 llvm-svn: 322419
* AMDGPU/SI: Add d16 support for buffer intrinsics.Changpeng Fang2018-01-1210-52/+446
| | | | | | | | | | Differential Revision: https://reviews.llvm.org/D38906 Reviewers: Matt and Brian. llvm-svn: 322402
* Silence GCC 7 warning by using an enum class.Florian Hahn2018-01-121-36/+42
| | | | | | | | | | | | | | | | | This silences the following GCC7 warning: lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp:142:30: warning: enumeral and non-enumeral type in conditional expression [-Wextra] return F != Colors.end() ? F->second : None; ~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~ Reviewers: amharc, RKSimon, davide Reviewed By: RKSimon, davide Differential Revision: https://reviews.llvm.org/D41003 llvm-svn: 322398
* [AArch64] Fix scheduling resources for post indexed loads and storesEvandro Menezes2018-01-121-2/+2
| | | | | | | | | Fix typos in the default scheduling resources when using the post indexed addressing modes. Differential revision: https://reviews.llvm.org/D40511 llvm-svn: 322392
* MC: Remove redundant `SetUsed` arguments in MCSymbol methodsSam Clegg2018-01-121-1/+1
| | | | | | | | | | | We can probably take this a step further since the only user of the isUsed flag is AsmParser it should probably be doing this explicitly. For now this is a step in the right direction though. Differential Revision: https://reviews.llvm.org/D41971 llvm-svn: 322386
* [X86] Remove unused isel pattern for zero extend from v16i1/v8i1 to ↵Craig Topper2018-01-121-5/+0
| | | | | | | | v16i32/v8i64. We have custom lowering on vzext that produces a vselect and a build vector. So zext never gets to isel. llvm-svn: 322381
* [PowerPC] Don't miscompile rotate+mask into an ANDIo if it can't recreate ↵Benjamin Kramer2018-01-121-0/+4
| | | | | | | | | the immediate I'm not even sure if this transform is ever worth it, but this at least stops the bleeding. llvm-svn: 322373
* [PowerPC] Zero-extend the compare operand for ATOMIC_CMP_SWAPNemanja Ivanovic2018-01-123-0/+61
| | | | | | | | | | | | Part of the fix for https://bugs.llvm.org/show_bug.cgi?id=35812. This patch ensures that the compare operand for the atomic compare and swap is properly zero-extended to 32 bits if applicable. A follow-up commit will fix the extension for the SETCC node generated when expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS. That will complete the bug fix. Differential Revision: https://reviews.llvm.org/D41856 llvm-svn: 322372
* Revert "[PowerPC] Manually schedule the prologue and epilogue"Stefan Pintilie2018-01-121-62/+6
| | | | | | | This reverts commit r322124 since some tests were broken by that patch. Will recommmit once the patch is fixed. llvm-svn: 322369
* [ARM GlobalISel] Map G_FMA to FPRDiana Picus2018-01-121-0/+14
| | | | llvm-svn: 322367
* [ARM GlobalISel] Legalize G_FMADiana Picus2018-01-121-0/+7
| | | | | | | | | | | For hard float with VFP4, it is legal. Otherwise, we use libcalls. This needs a bit of support in the LegalizerHelper for soft float because we didn't handle G_FMA libcalls yet. The support is trivial, as the only difference between G_FMA and other libcalls that we already handle is that it has 3 input operands rather than just 2. llvm-svn: 322366
* [ARM] Add codegen for SMMULR, SMMLAR and SMMLSRAndre Vieira2018-01-124-61/+121
| | | | | | | | | This patch teaches the Arm back-end to generate the SMMULR, SMMLAR and SMMLSR instructions from equivalent IR patterns. Differential Revision: https://reviews.llvm.org/D41775 llvm-svn: 322361
* [ARM] Fix erroneous availability of SMMLS for Armv7-MAndre Vieira2018-01-122-2/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D41855 llvm-svn: 322360
* [X86] Don't allow lods/stos/scas/cmps/movs to be parsed without a suffix and ↵Craig Topper2018-01-121-20/+20
| | | | | | | | only memory operand in at&t syntax. Without a register with a size being mentioned the instruction is ambiguous in at&t syntax. With Intel syntax the memory operation caries a size that can be used to disambiguate. llvm-svn: 322356
* [X86] Don't require suffix on 'clr' mnemonic in intel syntaxCraig Topper2018-01-121-4/+4
| | | | llvm-svn: 322355
* [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics.Craig Topper2018-01-121-6/+6
| | | | | | While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
* [X86] Disable sldtq parsing in 64-bit mode.Craig Topper2018-01-121-2/+2
| | | | llvm-svn: 322353
* [X86] Disable movsq/stosq/scasqcmpsq/lodsq parsing in 64-bit mode.Craig Topper2018-01-121-5/+10
| | | | llvm-svn: 322352
* [RISCV] Pass MCSubtargetInfo to print methods.Ana Pazos2018-01-123-9/+23
| | | | | | | | | | | | | | | | Summary: This change allows checking for ISA extensions in print methods. Reviewers: asb, niosHD Reviewed By: asb, niosHD Subscribers: llvm-commits, niosHD, asb, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal Differential Revision: https://reviews.llvm.org/D41503 llvm-svn: 322345
* Revert r322279 due to Skylake miscompile.David L. Jones2018-01-121-11/+0
| | | | | | | | | | | | Summary: This revision causes Skylake (and apparently, only Skylake) codegen to fail in certain cases. Details: https://bugs.llvm.org/show_bug.cgi?id=35918 Subscribers: sanjoy, llvm-commits Differential Revision: https://reviews.llvm.org/D41972 llvm-svn: 322335
* [hwasan] Stack instrumentation.Evgeniy Stepanov2018-01-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Very basic stack instrumentation using tagged pointers. Tag for N'th alloca in a function is built as XOR of: * base tag for the function, which is just some bits of SP (poor man's random) * small constant which is a function of N. Allocas are aligned to 16 bytes. On every ReturnInst allocas are re-tagged to catch use-after-return. This implementation has a bunch of issues that will be taken care of later: 1. lifetime intrinsics referring to tagged pointers are not recognized in SDAG. This effectively disables stack coloring. 2. Generated code is quite inefficient. There is one extra instruction at each memory access that adds the base tag to the untagged alloca address. It would be better to keep tagged SP in a callee-saved register and address allocas as an offset of that XOR retag, but that needs better coordination between hwasan instrumentation pass and prologue/epilogue insertion. 3. Lifetime instrinsics are ignored and use-after-scope is not implemented. This would be harder to do than in ASan, because we need to use a differently tagged pointer depending on which lifetime.start / lifetime.end the current instruction is dominated / post-dominated. Reviewers: kcc, alekseyshl Subscribers: srhines, kubamracek, javed.absar, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D41602 llvm-svn: 322324
* PeepholeOptimizer: Fix for vregs without defsMatthias Braun2018-01-111-4/+10
| | | | | | | | | | The PeepholeOptimizer would fail for vregs without a definition. If this was caused by an undef operand abort to keep the code simple (so we don't need to add logic everywhere to replicate the undef flag). Differential Revision: https://reviews.llvm.org/D40763 llvm-svn: 322319
* Make internal/private GVs implicitly dso_local.Rafael Espindola2018-01-111-1/+1
| | | | | | | | | | | | | | | | While updating clang tests for having clang set dso_local I noticed that: - There are *a lot* of tests to update. - Many of the updates are redundant. They are redundant because a GV is "obviously dso_local". This patch starts formalizing that a bit by requiring that internal and private GVs be dso_local too. Since they all are, we don't have to print dso_local to the textual representation, making it a bit more compact and easier to read. llvm-svn: 322317
* [arm] Implement Target Operand Flag MIR serialization.Evgeniy Stepanov2018-01-112-0/+35
| | | | | | | | | | Reviewers: efriedma, pcc Subscribers: aemerson, javed.absar, kristof.beyls, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D39975 llvm-svn: 322312
* [X86] Legalize 128/256 gathers/scatters on KNL by using widening rather than ↵Craig Topper2018-01-111-75/+38
| | | | | | | | sign extending the index. We can just widen the vectors with undef and zero extend the mask. llvm-svn: 322308
* [Hexagon] Fix building 64-bit vector from constant valuesKrzysztof Parzyszek2018-01-111-1/+1
| | | | | | The constants were aggregated in a reverse order. llvm-svn: 322303
* [Hexagon] Cast elements to correct type when creating constant vectorKrzysztof Parzyszek2018-01-111-1/+2
| | | | llvm-svn: 322301
* [Hexagon] Impose limits on container sizes in HexagonGenInsertKrzysztof Parzyszek2018-01-111-3/+20
| | | | | | | With over 300k virtual registers, the size of the data exceeded 12GB. Impose limits on how much information is collected. llvm-svn: 322299
* [Hexagon] Use SetVector when queuing nodes to scan in selectVectorConstantsKrzysztof Parzyszek2018-01-111-3/+4
| | | | llvm-svn: 322298
* X86: Refactor type-splitting to target-legal size vector to a helper functionZvi Rackover2018-01-111-32/+58
| | | | | | | | | | | | | | Summary: This is a preparatory step for D41811: refactoring code for breaking vector operands of binary operation to legal-types. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41925 llvm-svn: 322296
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