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* Delete dead code. NFC.Rafael Espindola2016-06-201-8/+0
| | | | llvm-svn: 273206
* Add a isPositionIndependent helper to ARMFastISel. NFC.Rafael Espindola2016-06-201-8/+13
| | | | llvm-svn: 273187
* [AArch64] Adjust the loop buffer size for Exynos M1 (NFC)Evandro Menezes2016-06-201-1/+1
| | | | llvm-svn: 273185
* AMDGPU: Preserve undef flag on vcc when shrinking v_cndmask_b32Matt Arsenault2016-06-201-16/+13
| | | | | | | | | The implicit operand is added by the initial instruction construction, so this was adding an additional vcc use. The original one was missing the undef flag the original condition had, so the verifier would complain. llvm-svn: 273182
* AMDGPU: Fold more custom nodes to undefMatt Arsenault2016-06-201-11/+40
| | | | | | | | | | | This will help sneak undefs past GVN into the DAG for some tests. Also add missing intrinsic for rsq_legacy, even though the node was already selected to the instruction. Also start passing the debug location to intrinsic errors. llvm-svn: 273181
* Generalize DiagnosticInfoStackSize to support other limitsMatt Arsenault2016-06-201-3/+11
| | | | | | | Backends may want to report errors on resources other than stack size. llvm-svn: 273177
* AMDGPU: Use correct method for determining instruction sizeMatt Arsenault2016-06-201-2/+4
| | | | llvm-svn: 273172
* Use shouldAssumeDSOLocal.Rafael Espindola2016-06-201-1/+3
| | | | | | With this ARM fast isel knows that PIE variable are not preemptable. llvm-svn: 273169
* AMDGPU: Add support for R_AMDGPU_REL32 relocationsTom Stellard2016-06-202-1/+8
| | | | | | | | | | Reviewers: arsenm, kzhuravl, rafael Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21401 llvm-svn: 273168
* Simplify. NFC.Rafael Espindola2016-06-201-6/+2
| | | | llvm-svn: 273167
* AMDGPU: Emit R_AMDGPU_ABS32_{HI,LO} for scratch buffer relocationsTom Stellard2016-06-201-4/+15
| | | | | | | | | | Reviewers: arsenm, rafael, kzhuravl Subscribers: rafael, arsenm, llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21400 llvm-svn: 273166
* [ARM] Enable isel of UMAALSam Parker2016-06-205-10/+133
| | | | | | | | | | TargetLowering and DAGToDAG are used to combine ADDC, ADDE and UMLAL dags into UMAAL. Selection is split into the two phases because it is easier to match the two patterns at those different times. Differential Revision: http://http://reviews.llvm.org/D21461 llvm-svn: 273165
* Add a isPositionIndependent predicate.Rafael Espindola2016-06-202-17/+20
| | | | | | | Reduces a bit of code duplication and clarify where we are interested just on position independence and no the location of the symbol. llvm-svn: 273164
* Removing an unused switch statement that has only a default label. This ↵Aaron Ballman2016-06-201-22/+16
| | | | | | happens to also eliminate an instance of switchception. NFC intended. llvm-svn: 273161
* [AARCH64] Add support for Broadcom VulcanPankaj Gode2016-06-203-1/+12
| | | | | | | | Adding core tuning support for new Broadcom Vulcan core (ARMv8.1A). Differential Revision: http://reviews.llvm.org/D21500 llvm-svn: 273148
* [AVX512] [AVX512/AVX][Intrinsics] Fix Variable Bit Shift Right Arithmetic ↵Igor Breger2016-06-207-11/+28
| | | | | | | | intrinsic lowering. Differential Revision: http://reviews.llvm.org/D20897 llvm-svn: 273138
* [X86] Pass the SDLoc and Mask ArrayRef down from lowerVectorShuffle through ↵Craig Topper2016-06-201-127/+78
| | | | | | all of the other routines instead of recreating them in the handlers for each type. NFC llvm-svn: 273137
* [X86] Use existing ArrayRef variable instead of calling SVOp->getMask() ↵Craig Topper2016-06-201-12/+12
| | | | | | repeatedly. Remove nearby else after return as well. NFC llvm-svn: 273136
* [X86] Avoid making a copy of a shuffle mask until we're sure we really need ↵Craig Topper2016-06-201-7/+7
| | | | | | to. And just use a SmallVector to do the copy because its easy. llvm-svn: 273135
* Reformat blank lines.NAKAMURA Takumi2016-06-205-14/+1
| | | | llvm-svn: 273131
* Trailing whitespace.NAKAMURA Takumi2016-06-202-6/+6
| | | | llvm-svn: 273130
* Untabify.NAKAMURA Takumi2016-06-209-29/+27
| | | | llvm-svn: 273129
* [X86][AVX512] Added 512-bit BITREVERSE tests and enabled AVX512BW lowering ↵Simon Pilgrim2016-06-191-0/+1
| | | | | | support llvm-svn: 273125
* Strip trailing whitespace. NFCI.Simon Pilgrim2016-06-191-2/+2
| | | | llvm-svn: 273124
* Fixed signed/unsigned warning.Simon Pilgrim2016-06-191-1/+1
| | | | llvm-svn: 273120
* [X86][SSE] Allow target shuffle combining to match masks with SM_Sentinel valuesSimon Pilgrim2016-06-191-22/+48
| | | | | | | | | | | | We currently only allow exact matches of shuffle mask patterns during target shuffle combining. This patch relaxes this to permit SM_SentinelUndef in the combined shuffle to always be accepted as well as allowing exact matching of the SM_SentinelZero value. I've adjusted some tests that were requiring exact shuffle masks to now include undef values. Differential Revision: http://reviews.llvm.org/D21495 llvm-svn: 273119
* [X86] Add an assert to ensure that a routine is only used with 128-bit ↵Craig Topper2016-06-191-2/+4
| | | | | | vectors. Reduce SmallVector size accordingly. llvm-svn: 273117
* [X86] Make is128BitLaneRepeatedShuffleMask correct the indices of the second ↵Craig Topper2016-06-191-15/+12
| | | | | | vector for the smaller mask. This removes some custom correction code and can potentially provide other benefits in the future. llvm-svn: 273116
* [X86] Remove a dead path through one of the shuffle lowering routines. It's ↵Craig Topper2016-06-191-24/+20
| | | | | | only called on single input shuffles masks already. Add an assert instead to verify. llvm-svn: 273115
* [X86] Pre-allocate a SmallVector instead of using push_back in a loop. NFCCraig Topper2016-06-191-6/+7
| | | | llvm-svn: 273114
* [X86] Use SmallVector::assign instead of resize to ensure we really start ↵Craig Topper2016-06-191-1/+1
| | | | | | | | with a vector of all -1s. Otherwise we're trusting the caller to pass the right thing. This should be no functional change with current code. llvm-svn: 273113
* [SPARC] Additional condition required for DelaySlot fixing erratum in ↵Chris Dewhurst2016-06-191-0/+7
| | | | | | revision r273108. llvm-svn: 273111
* [SPARC] Fixes for hardware errata on LEON processor.Chris Dewhurst2016-06-199-1/+449
| | | | | | | | | | Passes to fix three hardware errata that appear on some LEON processor variants. The instructions FSMULD, FMULS and FDIVS do not work as expected on some LEON processors. This change allows those instructions to be substituted for alternatives instruction sequences that are known to work. These passes only run when selected individually, or as part of a processor defintion. They are not included in general SPARC processor compilations for non-LEON processors or for those LEON processors that do not have these hardware errata. llvm-svn: 273108
* doesSetDirectiveSuppressesReloc -> doesSetDirectiveSuppressReloc, theJoerg Sonnenberger2016-06-181-1/+1
| | | | | | former is grammatically incorrect. llvm-svn: 273100
* test commit: remove trailing whitespaceZvi Rackover2016-06-181-1/+1
| | | | llvm-svn: 273094
* [mips] Emit a JALR with $rd equal to $zero, instead of a JR in MIPS32R6.Vasileios Kalintiris2016-06-181-15/+23
| | | | | | | | | | | | | | Summary: JR is an alias of JALR with $rd=0 in the R6 ISA. Also, this fixes recursive builds in MIPS32R6. Reviewers: dsanders, sdardis Subscribers: jfb, dschuff, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21370 llvm-svn: 273085
* AMDGPU: Fix kernel argument alignment impacting stack sizeMatt Arsenault2016-06-184-14/+29
| | | | | | | | Don't use AllocateStack because kernel arguments have nothing to do with the stack. The ensureMaxAlignment call was still changing the stack alignment. llvm-svn: 273080
* [X86][SSE4A] Autoupgrade and remove MOVNTSD/MOVNTSS intrinsicsSimon Pilgrim2016-06-181-4/+4
| | | | | | Required better annotation of the instruction defs upon removal of the builtin intrinsic pattern. llvm-svn: 273077
* [X86Subtarget] Use isPositionIndependent(). NFC.Davide Italiano2016-06-182-3/+7
| | | | | | Differential Revision: http://reviews.llvm.org/D21480 llvm-svn: 273071
* AMDGPU: Temporarily select trap to s_endpgmMatt Arsenault2016-06-173-0/+21
| | | | | | | | | | | | This should select to s_trap, but that requires additonal work to setup and enable the trap handler. For now emit s_endpgm so bugpoint stops getting stuck on the unsupported call to abort. Emit a warning that this will only terminate the wave and not really trap. llvm-svn: 273062
* AMDGPU/SI: Simplify code in SITargetLowering::LowerGlobalAddress()Tom Stellard2016-06-171-1/+1
| | | | | | This change were suggested in http://reviews.llvm.org/D21154. llvm-svn: 273059
* AMDGPU: Remove llvm.SI.tid intrinsicMatt Arsenault2016-06-173-9/+0
| | | | | | Mesa doesn't emit this for llvm >= 3.8 anymore. llvm-svn: 273050
* [X86] Add missing AVX512 anyext patterns.Michael Kuperstein2016-06-171-0/+8
| | | | | | | Add AVX512 anyext patterns for i16 and i64, modeled on the existing i8 and i32 patterns. llvm-svn: 273038
* Avoid duplicated map lookups. No functionality change intended.Benjamin Kramer2016-06-171-2/+3
| | | | llvm-svn: 273030
* ARM: take account of possible bundle when erasing an instruction.Tim Northover2016-06-171-1/+1
| | | | | | | Fortunately this appears to be the only ARM-specific pass that runs while bundles might be in play, so no other cases need modifying. llvm-svn: 273029
* Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass.James Y Knight2016-06-171-0/+2
| | | | | | | | | | | | | | | | | Many CPUs only have the ability to do a 4-byte cmpxchg (or ll/sc), not 1 or 2-byte. For those, you need to mask and shift the 1 or 2 byte values appropriately to use the 4-byte instruction. This change adds support for cmpxchg-based instruction sets (only SPARC, in LLVM). The support can be extended for LL/SC-based PPC and MIPS in the future, supplanting the ISel expansions those architectures currently use. Tests added for the IR transform and SPARCv9. Differential Revision: http://reviews.llvm.org/D21029 llvm-svn: 273025
* [Codegen] Change PICLevel.Davide Italiano2016-06-173-6/+6
| | | | | | | | | We convert `Default` to `NotPIC` so that target independent code can reason about this correctly. Differential Revision: http://reviews.llvm.org/D21394 llvm-svn: 273024
* Refactor and cleanup Assembly Parsing / LexingNirav Dave2016-06-174-17/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | Recommiting after fixing non-atomic insert to front of SmallVector in MCAsmLexer.h Add explicit Comment Token in Assembly Lexing for future support for outputting explicit comments from inline assembly. As part of this, CPPHash Directives are now explicitly distinguished from Hash line comments in Lexer. Line comments are recorded as EndOfStatement tokens, not Comment tokens to simplify compatibility with current TargetParsers. This slightly complicates comment output. This remove all lexing tasks out of the parser, does minor cleanup to remove extraneous newlines Asm Output, and some improvements white space handling. Reviewers: rtrieu, dwmw2, rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20009 llvm-svn: 273007
* [ARM] Strength reduce vectors to arrays.Benjamin Kramer2016-06-171-22/+10
| | | | | | No functionality change intended. llvm-svn: 273001
* [PPC] Strength-reduce SmallVectors into arrays.Benjamin Kramer2016-06-171-60/+36
| | | | | | No functionality change intended. llvm-svn: 272999
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