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* Mark MOVDQ(A/U)rm as ReMaterializable. Mark all MOVDQ(A/U) instructions as ↵Craig Topper2012-12-062-4/+9
| | | | | | neverHasSideEffects. llvm-svn: 169477
* [arm fast-isel] Make the fast-isel implementation of memcpy respect alignment.Chad Rosier2012-12-061-11/+22
| | | | | | rdar://12821569 llvm-svn: 169460
* Let targets provide hooks that compute known zero and ones for any_extendEvan Cheng2012-12-064-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and extload's. If they are implemented as zero-extend, or implicitly zero-extend, then this can enable more demanded bits optimizations. e.g. define void @foo(i16* %ptr, i32 %a) nounwind { entry: %tmp1 = icmp ult i32 %a, 100 br i1 %tmp1, label %bb1, label %bb2 bb1: %tmp2 = load i16* %ptr, align 2 br label %bb2 bb2: %tmp3 = phi i16 [ 0, %entry ], [ %tmp2, %bb1 ] %cmp = icmp ult i16 %tmp3, 24 br i1 %cmp, label %bb3, label %exit bb3: call void @bar() nounwind br label %exit exit: ret void } This compiles to the followings before: push {lr} mov r2, #0 cmp r1, #99 bhi LBB0_2 @ BB#1: @ %bb1 ldrh r2, [r0] LBB0_2: @ %bb2 uxth r0, r2 cmp r0, #23 bhi LBB0_4 @ BB#3: @ %bb3 bl _bar LBB0_4: @ %exit pop {lr} bx lr The uxth is not needed since ldrh implicitly zero-extend the high bits. With this change it's eliminated. rdar://12771555 llvm-svn: 169459
* Define new-value store instructions with base+immediate addressing modeJyotsna Verma2012-12-051-128/+53
| | | | | | using multiclass. llvm-svn: 169432
* Cost Model: change the default cost of control flow instructions (br / ret / ↵Nadav Rotem2012-12-051-1/+1
| | | | | | ...) to zero. llvm-svn: 169423
* Correct ARM NOP encodingDavid Sehr2012-12-051-1/+1
| | | | | | | | | | The encoding of NOP in ARMAsmBackend.cpp is missing a trailing zero, which causes the emission of a coprocessor instruction rather than "mov r0, r0" as indicated in the comment. The test also checks for the wrong encoding. http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121203/157919.html llvm-svn: 169420
* [NVPTX] Fix crash with unnamed struct argumentsJustin Holewinski2012-12-051-1/+1
| | | | | | Patch by Eric Holk llvm-svn: 169418
* Use multiclass to define store instructions with base+immediate offsetJyotsna Verma2012-12-051-138/+68
| | | | | | addressing mode and immediate stored value. llvm-svn: 169408
* Fix misplaced closing brace.Matthew Curtis2012-12-051-1/+2
| | | | llvm-svn: 169404
* Added a option to the disassembler to print immediates as hex.Kevin Enderby2012-12-052-11/+11
| | | | | | | | | | | | | | | | | | | | This is for the lldb team so most of but not all of the values are to be printed as hex with this option. Some small values like the scale in an X86 address were requested to printed in decimal without the leading 0x. There may be some tweaks need to places that may still be in decimal that they want in hex. Specially for arm. I made my best guess. Any tweaks from here should be simple. I also did the best I know now with help from the C++ gurus creating the cleanest formatImm() utility function and containing the changes. But if someone has a better idea to make something cleaner I'm all ears and game for changing the implementation. rdar://8109283 llvm-svn: 169393
* Simplified BLEND pattern matching for shuffles.Elena Demikhovsky2012-12-054-78/+68
| | | | | | Generate VPBLENDD for AVX2 and VPBLENDW for v16i16 type on AVX2. llvm-svn: 169366
* Add x86 isel lowering logic to form bit test with inverted condition. e.g.Evan Cheng2012-12-051-6/+17
| | | | | | | | | x ^ -1. Patch by David Majnemer. rdar://12755626 llvm-svn: 169339
* Appease GCC's -Wparentheses.Matt Beaumont-Gay2012-12-041-2/+2
| | | | | | (TIL that Clang's -Wparentheses ignores 'x || y && "foo"' on purpose. Neat.) llvm-svn: 169337
* ARM custom lower ctpop for vector types. Patch by Pete Couperus.Evan Cheng2012-12-041-0/+117
| | | | llvm-svn: 169325
* Define store instructions with base+register offset addressing modeJyotsna Verma2012-12-041-352/+116
| | | | | | using multiclass. llvm-svn: 169314
* Make NaCl naming consistent. The triple OSType is called NaCl and is representedEli Bendersky2012-12-042-2/+2
| | | | | | | | | textually as NativeClient. Also added a link to the native client project for readers unfamiliar with it. A Clang patch will follow shortly. llvm-svn: 169291
* Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count ↵Jyotsna Verma2012-12-043-17/+97
| | | | | | | | trailing/leading zeros) instructions. llvm-svn: 169287
* Add constant extender support to ALU32 instructions for V2.Jyotsna Verma2012-12-041-51/+79
| | | | llvm-svn: 169284
* This patch introduces initial-exec model support for thread-local storageBill Schmidt2012-12-0413-15/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on 64-bit PowerPC ELF. The patch includes code to handle external assembly and MC output with the integrated assembler. It intentionally does not support the "old" JIT. For the initial-exec TLS model, the ABI requires the following to calculate the address of external thread-local variable x: Code sequence Relocation Symbol ld 9,x@got@tprel(2) R_PPC64_GOT_TPREL16_DS x add 9,9,x@tls R_PPC64_TLS x The register 9 is arbitrary here. The linker will replace x@got@tprel with the offset relative to the thread pointer to the generated GOT entry for symbol x. It will replace x@tls with the thread-pointer register (13). The two test cases verify correct assembly output and relocation output as just described. PowerPC-specific selection node variants are added for the two instructions above: LD_GOT_TPREL and ADD_TLS. These are inserted when an initial-exec global variable is encountered by PPCTargetLowering::LowerGlobalTLSAddress(), and later lowered to machine instructions LDgotTPREL and ADD8TLS. LDgotTPREL is a pseudo that uses the same LDrs support added for medium code model's LDtocL, with a different relocation type. The rest of the processing is straightforward. llvm-svn: 169281
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-0449-100/+100
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* Move all operand definitions into HexagonOperands.tdJyotsna Verma2012-12-042-53/+57
| | | | llvm-svn: 169213
* Move generic Hexagon subtarget information into Hexagon.tdJyotsna Verma2012-12-042-64/+101
| | | | llvm-svn: 169212
* Remove the old TRI::ResolveRegAllocHint() and getRawAllocationOrder() hooks.Jakob Stoklund Olesen2012-12-042-270/+0
| | | | | | | These functions have been replaced by TRI::getRegAllocationHints() which provides the same capabilities. llvm-svn: 169192
* Classic JIT is still being supported by MIPS, along with MCJIT.Akira Hatanaka2012-12-033-11/+24
| | | | | | | | | This change adds endian-awareness to MipsJITInfo and emitWordLE in MipsCodeEmitter has become emitWord now to support both endianness. Patch by Petar Jovanovic. llvm-svn: 169177
* Functions in MipsCodeEmitter.cpp that expand unaligned loads/stores are deadAkira Hatanaka2012-12-031-103/+0
| | | | | | | | code. Removing it. Patch by Petar Jovanovic. llvm-svn: 169174
* Implement ARMBaseRegisterInfo::getRegAllocationHints().Jakob Stoklund Olesen2012-12-032-0/+65
| | | | | | | This provides the same functionality as getRawAllocationOrder() for the even/odd hints, but without the many constant register arrays. llvm-svn: 169169
* Define store instructions with base+immediate offset addressing modeJyotsna Verma2012-12-032-185/+78
| | | | | | using multiclass. llvm-svn: 169168
* Define load instructions with base+immediate offset addressing modeJyotsna Verma2012-12-031-203/+73
| | | | | | using multiclass. llvm-svn: 169153
* Define unsigned const-ext predicates.Jyotsna Verma2012-12-031-0/+128
| | | | llvm-svn: 169149
* Removing unnecessary 'else' statement from the predicates defined in ↵Jyotsna Verma2012-12-031-48/+12
| | | | | | HexagonOperards.td. llvm-svn: 169148
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-03181-798/+793
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Define signed const-ext predicates.Jyotsna Verma2012-12-031-0/+131
| | | | llvm-svn: 169117
* Codegen failure for vmull with small vectorsSebastian Pop2012-11-301-13/+74
| | | | | | | | | | | | | | | | | | | | | | | | | Codegen was failing with an assertion because of unexpected vector operands when legalizing the selection DAG for a MUL instruction. The asserting code was legalizing multiplies for vectors of size 128 bits. It uses a custom lowering to try and detect cases where it can use a VMULL instruction instead of a VMOVL + VMUL. The code was looking for input operands to the MUL that had been sign or zero extended. If it found the extended operands it would drop the sign/zero extension and use the original vector size as input to a VMULL instruction. The code assumed that the original input vector was 64 bits so that after dropping the extension it would fit directly into a D register and could be used as an operand of a VMULL instruction. The input code that trigger the failure used a vector of <4 x i8> that was sign extended to <4 x i32>. It was not safe to drop the sign extension in this case because the original vector is only 32 bits wide. The fix is to insert a sign extension for the vector to reach the required 64 bit size. In this particular example, the vector would need to be sign extented to a <4 x i16>. llvm-svn: 169024
* Use multiclass for the load instructions with MEMri operand.Jyotsna Verma2012-11-301-184/+66
| | | | llvm-svn: 169018
* This patch fixes the Altivec addend construction for the fused multiply-addAdhemerval Zanella2012-11-301-5/+7
| | | | | | | | | | | | | | | instruction (vmaddfp) to conform with IEEE to ensure the sign of a zero result when resulting product is -0.0. The -0.0 vector addend to vmaddfp is generated by a creating a vector with full bits sets and then shifting each elements by 31-bits to the left, resulting in a vector of 0x80000000 (or -0.0 as float). The 'buildvec_canonicalize.ll' was adjusted to reflect this change and the 'vec_mul.ll' was complemented with the float vector multiplication test. llvm-svn: 168998
* Switch LLVM_USE_RVALUE_REFERENCES to LLVM_HAS_RVALUE_REFERENCES.Chandler Carruth2012-11-301-1/+1
| | | | | | | | | | | | | | Rationale: 1) This was the name in the comment block. ;] 2) It matches Clang's __has_feature naming convention. 3) It matches other compiler-feature-test conventions. Sorry for the noise. =] I've also switch the comment block to use a \brief tag and not duplicate the name. llvm-svn: 168996
* Use multiclass for the store instructions with MEMri operand.Jyotsna Verma2012-11-302-163/+64
| | | | llvm-svn: 168983
* Use multiclass for the load instructions with 'base + register offset'Jyotsna Verma2012-11-301-277/+97
| | | | | | addressing mode. llvm-svn: 168976
* Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby2012-11-291-1/+7
| | | | | | which would then cause an assert when printed. rdar://11437956 llvm-svn: 168960
* Add cortex-a5 subtarget to the supported ARM architecturesQuentin Colombet2012-11-292-1/+12
| | | | llvm-svn: 168933
* rdar://12100355 (part 1)Shuxin Yang2012-11-293-1/+20
| | | | | | | | | | | | | | This revision attempts to recognize following population-count pattern: while(a) { c++; ... ; a &= a - 1; ... }, where <c> and <a>could be used multiple times in the loop body. TODO: On X8664 and ARM, __buildin_ctpop() are not expanded to a efficent instruction sequence, which need to be improved in the following commits. Reviewed by Nadav, really appreciate! llvm-svn: 168931
* Use multiclass for 'transfer' instructions.Jyotsna Verma2012-11-292-80/+98
| | | | llvm-svn: 168929
* Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.Silviu Baranga2012-11-294-12/+102
| | | | llvm-svn: 168886
* Allow targets to prefer TypeSplitVector over TypePromoteInteger when ↵Justin Holewinski2012-11-292-0/+7
| | | | | | | | computing the legalization method for vectors For some targets, it is desirable to prefer scalarizing <N x i1> instead of promoting to a larger legal type, such as <N x i32>. llvm-svn: 168882
* I changed hasAVX() to hasFp256() and hasAVX2() to hasInt256() in ↵Elena Demikhovsky2012-11-292-102/+104
| | | | | | | | X86IselLowering.cpp. The logic was not changed, only names. llvm-svn: 168875
* Define signed const-ext immediate operands and their predicates.Jyotsna Verma2012-11-282-0/+122
| | | | llvm-svn: 168810
* ARM: Implement CanLowerReturn so large vectors get expanded into sret.Benjamin Kramer2012-11-282-0/+17
| | | | | | Fixes 14337. llvm-svn: 168809
* Fix initial frame state on powerpc64.Ulrich Weigand2012-11-281-1/+1
| | | | | | | | | The createPPCMCAsmInfo routine used PPC::R1 as the initial frame pointer register, but on PPC64 the 32-bit R1 register does not have a corresponding DWARF number, causing invalid CIE initial frame state to be emitted. Fix by using PPC::X1 instead. llvm-svn: 168799
* Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen2012-11-284-12/+12
| | | | | | This class has been merged into its super-class TargetInstrInfo. llvm-svn: 168760
* Move Target{Instr,Register}Info.cpp into lib/CodeGen.Jakob Stoklund Olesen2012-11-283-338/+0
| | | | | | | | | | | | | | | | The Target library is not allowed to depend on the large CodeGen library, but the TRI and TII classes provide abstract interfaces that require both caller and callee to link to CodeGen. The implementation files for these classes provide default implementations of some of the hooks. These methods may need to reference CodeGen, so they belong in that library. We already have a number of methods implemented in the TargetInstrInfoImpl sub-class because of that. I will merge that class into the parent next. llvm-svn: 168758
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